Low noise, low power 5-Channel sonar signal conditioning receiver with 1.5 MS/s - 12.5 MS/s 16-bit sigma-delta ADC for ocean acoustic measurements
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This paper presents a design of 5-channel receiver for ocean acoustic measurement in a very noisy environment. When measuring the distance in the ocean with the sonar signal, the input signal level to the receiver is drastically changed depending on the distance between the transmitter and objects. Thus, the receiver with high sensitivity and wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for high sensitivity of the receiver, low noise pre-amplifier is proposed and implemented achieving the noise of 29.6 nV/√Hz at 50 kHz. In addition, Sigma-Delta Analog-to-Digital Converter (SD ADC) with variable sampling rates is proposed by using clock splitting technique in the Sigma-Delta Modulator (SDM) core. Also, the decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled to reduce the power consumption. Thanks to these techniques in the SD ADC, we can implement the reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for multi-channel application, Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The 5-channel receiver in this paper is implemented in 0.18μm CMOS process and die area is 14.44 mm2. The total power consumption of this chip is 46.8 mW under the supply voltage of 2.4 V. The measured sensitivity and dynamic range are -100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively. The maximum phase error between 5 channels is measured to be ± 0.8 °.
Abstract
This paper presents a design of 5-channel receiver for ocean acoustic measurement in a very noisy environment. When measuring the distance in the ocean with the sonar signal, the input signal level to the receiver is drastically changed depending on the distance between the transmitter and objects. Thus, the receiver with high sensitivity and wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for high sensitivity of the receiver, low noise pre-amplifier is proposed and implemented achieving the noise of 29.6 nV/√Hz at 50 kHz. In addition, Sigma-Delta Analog-to-Digital Converter (SD ADC) with variable sampling rates is proposed by using clock splitting technique in the Sigma-Delta Modulator (SDM) core. Also, the decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled to reduce the power consumption. Thanks to these techniques in the SD ADC, we can implement the reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for multi-channel application, Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The 5-channel receiver in this paper is implemented in 0.18μm CMOS process and die area is 14.44 mm2. The total power consumption of this chip is 46.8 mW under the supply voltage of 2.4 V. The measured sensitivity and dynamic range are -100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively. The maximum phase error between 5 channels is measured to be ± 0.8 °.
참고문헌 (13)
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