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A Low Phase Noise Integer-N Frequency Synthesizer for 2.4GHz ZigBee Application

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초록

A low phase noise and low power consumption integer-N frequency synthesizer for ZigBee application (IEEE 802.15.4) in the frequency range of 2.39-2.51GHz with channel spacing of 5MHz is designed through Samsung CMOS 65nm process. The phase noise and low power consumption are important factors for phase locked loop (PLL) design considering RF transceiver performance. The phase noise characteristics of proposed frequency synthesizer can be improved by dividing the large tuning range into a sub-band range with a small gain of VCO. Phase noise can be reduced by choosing the appropriate code value assigned to the desired channel using AFC (auto frequency calibration). Also, AFC’s power consumption could be decreased in coarse tuning mode. It consumes 14 mW during the coarse tuning mode and 11 mW during the fine tuning mode at 1.2V supply, respectively. It occupies an area of 1.73 mm × 1.73 mm including PADs. The simulated phase noise characteristic of the frequency synthesizer is -125dBc/Hz at 1 MHz offset from the carrier.

Abstract

A low phase noise and low power consumption integer-N frequency synthesizer for ZigBee application (IEEE 802.15.4) in the frequency range of 2.39-2.51GHz with channel spacing of 5MHz is designed through Samsung CMOS 65nm process. The phase noise and low power consumption are important factors for phase locked loop (PLL) design considering RF transceiver performance. The phase noise characteristics of proposed frequency synthesizer can be improved by dividing the large tuning range into a sub-band range with a small gain of VCO. Phase noise can be reduced by choosing the appropriate code value assigned to the desired channel using AFC (auto frequency calibration). Also, AFC’s power consumption could be decreased in coarse tuning mode. It consumes 14 mW during the coarse tuning mode and 11 mW during the fine tuning mode at 1.2V supply, respectively. It occupies an area of 1.73 mm × 1.73 mm including PADs. The simulated phase noise characteristic of the frequency synthesizer is -125dBc/Hz at 1 MHz offset from the carrier.

참고문헌 (11)

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  2. Rangakrishnan Srinivasan, "A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications", IEEE International Symposium on Circuit and Systems, pp.429~432 (2007)
  3. Aktas, M. Ismail, "CMOS PLL calibration techniques", IEEE Circuit and Devices Magazine, 20, pp.6~11 (2004)
  4. Chan-Young Jeong, "A fast automatic frequency calibration technique for a 2-6GHz frequency synthesizer", International Journal of Curcuit Theory and Applications, pp.309~320 (2014)
  5. Li Z, "A low-phase noise and low-power multiband CMOS voltage-controlled oscillator", IEEE Journal of Solid-State Circuits, 40(6), pp.1296~1302 (2005)
  6. B. Razavi, "Challenges in the design of frequency synthesizers for wireless applications", IEEE Custom Integrated Circuits Conf, pp.395~402 (1997)
  7. S. Pellerano, "A 13.5-mW 5-GHz frequency synthesizer with dynamic-Logic frequency divider", IEEE J. Solid-State Circuits,, 39(2), pp.378~383 (2004)
  8. F. Herzel, "An integrated CMOS RF synthesizer for 802. 11a wireless LAN", IEEE J. Solid-State Circuits, 38(10), pp.1767~1770 (2003)
  9. I. Bouras, "A digitally calibrated 5.15–5.825GHz transceiver for 802.11a wireless LANs” 0.18 m CMOS", IEEE Int. Solid-State Circuits Conf, pp.352~353 (2003)
  10. P. Zhang, "A direct conversion CMOS transceiver for IEEE 802.11a WLANs", IEEE Int. Solid-State Circuits Conf, pp.354~355 (2003)
  11. Y-S. Choi, "Gain-Boosting charge Pump for current Matching in Phase-Locked Loop", IEEE Transactions on Circuits and Systems II: Express Briefs, pp.1022~1025 (2006)

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