DTV 튜너를 위한 CMOS Fractional-N 주파수합성기
A CMOS Fractional-N Frequency Synthesizer for DTV Tuners
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초록
The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a 0.18μm CMOS process. It satisfies the DTV(ATSC) frequency band(54∼806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6∼3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59∼94MHz(±17.7MHz/V,±23%) and frequency steps of 26∼42.5MHz(±8.25MHz/V,±24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than 10μsec. It consumes 20∼23mA from a 1.8V supply, and the chip size including PADs is 2.0mm×1.8mm.
Abstract
The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a 0.18μm CMOS process. It satisfies the DTV(ATSC) frequency band(54∼806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6∼3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59∼94MHz(±17.7MHz/V,±23%) and frequency steps of 26∼42.5MHz(±8.25MHz/V,±24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than 10μsec. It consumes 20∼23mA from a 1.8V supply, and the chip size including PADs is 2.0mm×1.8mm.
참고문헌 (15)
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