High-efficiency analog front-end design of passive NFC tag based on 65nm
2
조회
0
다운로드
0
인용
0
참고문헌
초록
The high-efficiency NFC AFE(Analog Front-End) was proposed and implemented in 65nm CMOS process. We proposed the novelty architecture of Envelope Detector which is the most important block in passive mode tag because those generate their own power. The Envelope Detector generating negative voltage and it can generate the negative voltage of -0.68V that is used for body bias and can detect the small voltage swing of 0.5V. The area of the high-efficiency NFD AFE is 1.9mmx2mm and it is very small compared with the conventional NFC AFE. The digital part of NFC is also verified by FPGA board. So the proposed NFC tag is feasible for many applications.
Abstract
The high-efficiency NFC AFE(Analog Front-End) was proposed and implemented in 65nm CMOS process. We proposed the novelty architecture of Envelope Detector which is the most important block in passive mode tag because those generate their own power. The Envelope Detector generating negative voltage and it can generate the negative voltage of -0.68V that is used for body bias and can detect the small voltage swing of 0.5V. The area of the high-efficiency NFD AFE is 1.9mmx2mm and it is very small compared with the conventional NFC AFE. The digital part of NFC is also verified by FPGA board. So the proposed NFC tag is feasible for many applications.
참고문헌 (12)
- Yan Lu, "A 13.56MHz Fully Integrated 1X", 2X Active Rectifier with Compensated Bias Current for Inductively Powered Devices, 2013, 66~67
- Jong-Wook Lee, "A Fully Integrated EPC Gen-2 UHF-Band Passive Tag IC Using an Efficient Power Management Technique", IEEE Transactions on Industrial Electronics, 61(6), pp.2922~2932 (2014)
- Jung-Hyun Cho, "An NFC transceiver using an inductive powered receiver for passive, active, RW and RFID modes", IEEE, International SoC Design Conference (ISOCC), pp.456~459 (2009)
- 조정현, "단일 칩 NFC 트랜시버의 설계", 전자공학회논문지 - SD, 44(1), pp.68~75 (2007), 대한전자공학회
- "IDEC NEWSLETTER" (2006)[URL]
- Guangjie Cai, "A 2.4pj", bit ASK Demodulator with 100% Modulation Rate for 13.56MHz NFC, IEEE International Symposium on Circuits and Systems (ISCAS), pp.2014[DOI]
- 심현철, "UHF 대역 RFID 태그 칩을 위한저전력 CMOS 아날로그 Front-End 회로 설계", 전자공학회논문지 - SD, 45(6), pp.28~36 (2008), 대한전자공학회
- G.N. Jadjav, "UHF class-4 active two-way RFID tag for a hybrid RFID-based system", IEEE, RF and Microwave Conference(RFM), pp.337~342 (2011)
- 김주승, "Highly Efficient Envelope-Tracking Modulator Over Wide Output Power Range for Dual-Mode Power Amplifier", IDEC Journal of Integrated Circuits and Systems, 1(1), pp.28~34 (2015), 반도체설계교육센터
- 박홍준, "CMOS 아날로그 집적회로 설계" (2010), 시그마프레스
- J.-W.Leel, "A fully integrated high security NFC target IC using 0. 18um CMOS process", IEEE, ESSCIRC, pp.551~554 (2011)
- NFC FORUM, "NFC Digital protocol Technical Specification", ~ (2010)