A design of Envelope Detector and DC Rectifier for 8~100% ASK Communication
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초록
The passive multi-mode NFC AFE(Analog Front-End) was proposed and implemented in 65nm CMOS process. We proposed the novelty architecture of DC Rectifier and Envelope Detector which are the most important blocks in passive mode because those generate their own power. The Complementary DC Rectifier is proposed and it is more efficient compared with the conventional DC Rectifier composed of NMOS only or PMOS only. The Envelope Detector generating negative voltage is proposed and it can generate the negative voltage of -0.68V that is used for body bias. The area of the passive multi-mode NFC AFE is 0.19mm×2mm and it is very small compared with the conventional NFC AFE.
Abstract
The passive multi-mode NFC AFE(Analog Front-End) was proposed and implemented in 65nm CMOS process. We proposed the novelty architecture of DC Rectifier and Envelope Detector which are the most important blocks in passive mode because those generate their own power. The Complementary DC Rectifier is proposed and it is more efficient compared with the conventional DC Rectifier composed of NMOS only or PMOS only. The Envelope Detector generating negative voltage is proposed and it can generate the negative voltage of -0.68V that is used for body bias. The area of the passive multi-mode NFC AFE is 0.19mm×2mm and it is very small compared with the conventional NFC AFE.
참고문헌 (13)
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