A 5-5.8 GHz Sub-2 dB NF CMOS Low Noise Amplifier with Bandwidth Extension and Noise Optimization Techniques

Abstract

A 5-5.8 GHz sub-2 dB noise figure (NF) CMOS low noise amplifier (LNA) with bandwidth extension and noise optimization techniques is proposed for WiFi applications. The proposed LNA was based on the cascode feedback topology for broadband input impedance matching characteristic, and adopted the double-stacked LC resonators as an output load in order to extend the gain-bandwidth from 5 to 5.8 GHz. In addition, the input matching network was designed to provide the optimum source impedance for the minimum noise figure (NFmin) over wide frequency range (5-5.8 GHz) using the source-pull simulation. Owing to the proposed noise optimization technique, the NF of the LNA can be close to NFmin over wide operating frequency range. The proposed LNA was designed using a 65-nm CMOS process. It showed a NF of less than 2 dB, a power gain (S21) of greater than 15 dB, and an input and output return loss (S11 and S22) of less than -10 dB over 5-5.8 GHz in the post-layout simulation. The simulated 2 dB gain bandwidth and input-referred third-order intercept point (IIP3) were 1399 MHz and -4.1 dBm, respectively, with dc power consumption of 7.4 mW.