A Linear CMOS Power Amplifier with Inter-stage Transformer
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We designed the power amplifier using CMOS pro cess. The gain reduction by the bonded-wire and the low breakdown voltage problem of the device in the CMOS process are alleviated by applying a differential cascode structure. In order to reflect the distortion of the linearity in the driver stage, it is designed as 2-stage. An RC-feedback network was applied to the power stage to achieve low output impedance as well as high output power and efficiency. It is implemented using Magna/SKhynix 0.18µm 1P6M CMOS process. The total size is 0.7 x 1.7 mm² including pads. No oscillation occurred in all the measured bands. As a measurement results, output power and PAE were about 23 dBm / 13% in the CW signal, 20 dBm / 10% in the LTE signal, 18 dBm / 3% in the WLAN signal.
Abstract
We designed the power amplifier using CMOS pro cess. The gain reduction by the bonded-wire and the low breakdown voltage problem of the device in the CMOS process are alleviated by applying a differential cascode structure. In order to reflect the distortion of the linearity in the driver stage, it is designed as 2-stage. An RC-feedback network was applied to the power stage to achieve low output impedance as well as high output power and efficiency. It is implemented using Magna/SKhynix 0.18µm 1P6M CMOS process. The total size is 0.7 x 1.7 mm² including pads. No oscillation occurred in all the measured bands. As a measurement results, output power and PAE were about 23 dBm / 13% in the CW signal, 20 dBm / 10% in the LTE signal, 18 dBm / 3% in the WLAN signal.
참고문헌 (7)
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