Design of a 10-bit SAR ADC with Enhancement of Linearity on C-DAC Array
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초록
This paper proposes design of a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) reducing device mismatching property driven by MSB node of C-DAC array divided into 4 equal parts. It improves linearity by adding switch for reducing mismatch of MSB node which is the highest portion of mismatch in C-DAC array. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 850um х 650um. It consumes 66.4uW and achieves an ENOB of 9.3 bits at sampling frequency 800kS/s and power supply of 1.8V. The Figure of Merit (FOM) is simulated to be 134.31fJ/step.
Abstract
This paper proposes design of a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) reducing device mismatching property driven by MSB node of C-DAC array divided into 4 equal parts. It improves linearity by adding switch for reducing mismatch of MSB node which is the highest portion of mismatch in C-DAC array. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 850um х 650um. It consumes 66.4uW and achieves an ENOB of 9.3 bits at sampling frequency 800kS/s and power supply of 1.8V. The Figure of Merit (FOM) is simulated to be 134.31fJ/step.
참고문헌 (13)
- Guan-Ying Huang, "A 1-μW 10-bit 200-kS", s SAR ADC With a Bypass Window for Biomedical Applications, pp.47, 2783~2795
- Yung-Hui Chung, "A 12-bit 8.47-fJ", Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS, 2015, pp.62(1), ~
- Yuan Zhou, "A 12 bit 160 MS", s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector, 2015, pp.50(4), ~
- Howard Tang, "A 1.33 uW 8.02-ENOB 100 kS", s Successive Approximation ADC With Supply Reduction Technique for Implantable Retinal Prosthesis, 2015, pp.50(4), ~
- J. Um, "A digital- domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits", IEEE trans. on Circuit and System I, 60(11), pp.2845~2856 (2013)
- Y. Chen, "Split capacitor DAC mismatch calibration in successive approximation ADC", Proc. IEEE Custom Integr. Circuits Conf., pp.279~282 (2009)
- Y Chen, "Split capacitor DAC mismatch calibration in successive approximation ADC", IEEE CICC, pp.279~282 (2009)
- J. Y. Um, "Digital-domain calibration of split-CDAC with no extra calibration DAC for a differential- type SAR ADC", Proc. IEEE Asian Solid-State Circuits Conf., pp.77~80 (2011)
- D. Shi, "A 6-bit 500MS", s CMOS A, The Journal of Korean Information and Communications Society, pp.2013, 38(4)[DOI]
- Behazade Razavi, "Design of Analog CMOS Integrated Circuits" (2001), Macgaw-Hill Companies, Inc.
- Dai Zhang, "Design of Ultra-Low-Power Analog-to-Digital Converters", Linkoping Studies in Science and Technology, Thesis No. 1548, ~
- Raheleh Hedayati, "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology", Master, Electronic Devices, Dept. of Electrical Engineering
- Jin-Yi Lin, "A 0.3 V 10-bit 1.17f SAR ADC With Merge and Split Switching in 90nm CMOS", IEEE Transactions on and systems, 62(1) (2015)