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A DC-DC Converter with Voltage-Mode PWM Control

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초록

- In this paper, a voltage-mode PWM controlled buck converter is addressed. It consists of a pair of fullyintegrated switches, an LC filter, a type 3 compensation loop, an internal ramp & clock generator, and a dead-time generator. A portion of output is taken with a resistive divider and subtracted from an external reference voltage to generate an error voltage. Then the error voltage is compared with a ramp signal, creating a PWM signal for controlling high-side and low-side switches. This buck converter is fabricated in 0.18-μm CMOS process and area of control block is 0.28 mm2. Input voltage is 3.3 V and target output voltage is 1.8 V. Peak measured power conversion efficiency is 94.38% at 150 mA constant load condition. In a load transient testing from 100 mA to 300 mA, overshoot settling time measures 17.44 us. Overshoot magnitude is 68 mV and undershoot settling time and magnitude is 8.56 us and 60.8 mV, respectively.

Abstract

- In this paper, a voltage-mode PWM controlled buck converter is addressed. It consists of a pair of fullyintegrated switches, an LC filter, a type 3 compensation loop, an internal ramp & clock generator, and a dead-time generator. A portion of output is taken with a resistive divider and subtracted from an external reference voltage to generate an error voltage. Then the error voltage is compared with a ramp signal, creating a PWM signal for controlling high-side and low-side switches. This buck converter is fabricated in 0.18-μm CMOS process and area of control block is 0.28 mm2. Input voltage is 3.3 V and target output voltage is 1.8 V. Peak measured power conversion efficiency is 94.38% at 150 mA constant load condition. In a load transient testing from 100 mA to 300 mA, overshoot settling time measures 17.44 us. Overshoot magnitude is 68 mV and undershoot settling time and magnitude is 8.56 us and 60.8 mV, respectively.

참고문헌 (8)

  1. Hoi Lee, "Fundamentals of Switched-Mode Power-Converter Design", IEEE Int. Solid-State Circuits Conf, pp.8~ (2018)
  2. Linear Regulator Design Guide for LDOs, "Bruce Hunter", Texas Instruments Application, ~, pp.SLVA118A
  3. Paul Paglia, "LDO Thermal considerations", Microchip Application Note AN762, ~
  4. Tom Van Breussegem, "CMOS Integrated Capacitive DC-DC Converters", pp.21~ (2013), Springer
  5. Amir M. Rahimi, "Application Note AN-1162 – Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier", International Rectifier Corporation (now an Infineon Business), ~
  6. Wing-Hung Ki, "IC Design of Power Management Circuits", IEEE Int. Symp. On Integrated Circuits, pp.15~16 (2009)
  7. C. J. Chuang, "An efficient fast response hysteresis buck converter with adaptive synthetic ripple modulator", 8th International Conference on Power Electronics - ECCE Asia, pp.620~627 (2011)
  8. T. Lee, "A CMOS buck converter with PFM", hysteretic mode, 2016 (2016), 347~348

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