Compact Noise and Linearity Model of a Dynamic Amplifier for Behavioral ADC Modeling
1
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
This paper introduces the behavioral model of dynamic amplifier which is designed in 28nm CMOS process. First, the gain of the dynamic amplifier is analyzed from various perspectives, such as input common mode voltage, input differential mode voltage and pulse width. Next, the method that is to implement the gain value non-linearity model of the amplifier and the noise model through SPICE simulations is described in detail. The gain model including nonlinearity exhibits –6.7%∼5.4% of modeling error rate and the noise model shows –11.2%∼13.5% of modeling error rate. The proposed model in this paper is applied to the 1.1Gs/s 7-bit pipelined ADC design verification to confirm the reliability. In addition, design efficiency of the proposed behavioral model is described.
Abstract
This paper introduces the behavioral model of dynamic amplifier which is designed in 28nm CMOS process. First, the gain of the dynamic amplifier is analyzed from various perspectives, such as input common mode voltage, input differential mode voltage and pulse width. Next, the method that is to implement the gain value non-linearity model of the amplifier and the noise model through SPICE simulations is described in detail. The gain model including nonlinearity exhibits –6.7%∼5.4% of modeling error rate and the noise model shows –11.2%∼13.5% of modeling error rate. The proposed model in this paper is applied to the 1.1Gs/s 7-bit pipelined ADC design verification to confirm the reliability. In addition, design efficiency of the proposed behavioral model is described.
참고문헌 (10)
- B. Malki, "A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS", s pipelined SAR ADC, 2014 (2014), 215~218
- M. Zhang, "Gain-boosted dynamic amplifier for pipelined-SAR ADCs", Electronics Letters, 53(11) (2017)
- H. Huang, "A noninterleaved 12-b 330-MS", s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving sub-1-dB SNDR variation, 2017, pp.52(12), 3235~3247
- C-C. Liu, "A 0.46mW 5MHz-BW 79.7dB-SNDR Noise-Shaping SAR ADC with Dynamic Amplifier-Based FIR-IIR Filter", IEEE International Solid-State Circuit Conference (ISSCC) Digest of Technical Papers, pp.466~467 (2017)
- C. C. Lee, "A SAR-assisted two-stage pipeline ADC", IEEE J. Solid-State Circuits, 46(4), pp.859~869 (2011)
- "X-model"[URL]
- J. Lin, "A 15.5 dB, wide signal swing, dynamic amplifier using a commonmode voltage detection technique", Proc. IEEE ISCAS, pp.21~24 (2011)
- B. Razavi, "Design of analog CMOS Integrated circuits", ~
- "IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std 1241-2000", ~ (2000)