Design of a hybrid SAR-cyclic ADC with gain-error calibration
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초록
Low-power consumption and medium resolution analog-to-digital converters (ADCs) operate at several tens of MS/s. These are crucial factors for portable wireless communication applications. In this paper, SAR-assisted cyclic ADC features the low-power merit of successive approximation (SAR) ADC and small chip area of cyclic ADC. It improves an intrinsic limitation of ADCs conversion speed. The power consumption of the operational amplifier for cyclic ADC is reduced dramatically by using a new simple gain-error calibration technique. The MSB 4-b is converted by cyclic ADC and it only needs 2 cycles by multiplying digital to analog converter (MDAC) operation. Residue voltage generated at the end of the 2nd cycle conversion of cyclic ADC is converted by 6-b SAR operation.
Abstract
Low-power consumption and medium resolution analog-to-digital converters (ADCs) operate at several tens of MS/s. These are crucial factors for portable wireless communication applications. In this paper, SAR-assisted cyclic ADC features the low-power merit of successive approximation (SAR) ADC and small chip area of cyclic ADC. It improves an intrinsic limitation of ADCs conversion speed. The power consumption of the operational amplifier for cyclic ADC is reduced dramatically by using a new simple gain-error calibration technique. The MSB 4-b is converted by cyclic ADC and it only needs 2 cycles by multiplying digital to analog converter (MDAC) operation. Residue voltage generated at the end of the 2nd cycle conversion of cyclic ADC is converted by 6-b SAR operation.
참고문헌 (11)
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