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A Proposal of Methodologies for Implementing Digital Chips in the Latest Processes

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In this paper, design methodologies suitable for implementing digital systems at various processes are suggested. Important issues such as Multi Corner Multi Mode, Hierarchical Design, adoption of CCS model, and changes in design flow must be considered for ultra-fine processes. The Cortex-M0 SoC Platform is implemented, taking into account theses important issues, and the results using various digital libraries are compared. All implemented platforms meet specifications and operate normally with both hardware and software. The fastest clock cycle that can be synthesized is 4ns for Samsung 28nm process.

Abstract

In this paper, design methodologies suitable for implementing digital systems at various processes are suggested. Important issues such as Multi Corner Multi Mode, Hierarchical Design, adoption of CCS model, and changes in design flow must be considered for ultra-fine processes. The Cortex-M0 SoC Platform is implemented, taking into account theses important issues, and the results using various digital libraries are compared. All implemented platforms meet specifications and operate normally with both hardware and software. The fastest clock cycle that can be synthesized is 4ns for Samsung 28nm process.

참고문헌 (4)

  1. "Design Compiler User guide"[URL]
  2. "IC Compiler 2 User guide"[URL]
  3. Park, J. W., "Designing Neuromorphic Processor with On-Chip Learning", Journal of Integrated Circuits and Systems, 6(2) (2020)
  4. "Arm University Program"[URL]

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