Voltage Island Partitioning Based Floorplanning Algorithm
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As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.
Abstract
As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.
참고문헌 (6)
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- 신영수, "Architecting voltage islands in core-based System-on-a-Chip designs", Proc. Int`l Symp. on Low Power Electronics and Design (ISLPED), pp.180~185 (2004), ACM Press
- W. -P. Lee, "Voltage island aware floorplanning for power and timing optimization", in Proc. IEEE, 2006, 389~394
- Y. -C. Chang, "B*-trees: a new representation for non-slicing floorplans", in Proc. Design Automat. Conf., pp.458~463 (2000)