A High Current Efficiency CMOS LDO Regulator with Low Power Consumption and Small Output Voltage Variation
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In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier’s Bandwidth is 50.8MHz and its phase margin is 59.2˚. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from -40˚C to 125˚C we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a 1µF output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in 0.35µm CMOS process.
Abstract
In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier’s Bandwidth is 50.8MHz and its phase margin is 59.2˚. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from -40˚C to 125˚C we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a 1µF output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in 0.35µm CMOS process.
참고문헌 (17)
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