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채널 길이의 변화에 따른 단일 게이트 피드백 전계효과 트랜지스터의 메모리 윈도우 특성

Effect of Channel Length Variation on Memory Window Characteristics of single-gated feedback field-effect transistors

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초록

본 연구에서는 3차원 소자 시뮬레이션을 통하여 단일 게이트 피드백 전계효과 트랜지스터의 전기적 특성과 채널 길이에 따른 메모리 윈도우 특성 변화를 확인하였다. 소자의 채널 길이는 50 nm에서 100 nm까지 변화시켜가며 시뮬레이션을 수행하였다. 시뮬레이션 결과 0에 가까운 문턱전압이하 기울기(< 1 mV/dec)와 ∼1.27×1010의 Ion/Ioff 비율을 얻었다. 또한 메모리 윈도우를 확인한 결과 채널 길이 50 nm의 소자는 0.31 V의 메모리 윈도우가 생성되었으나 채널 길이 100 nm의 소자는 메모리 윈도우가 생성되지 않았다.

Abstract

In this study, we examined the simulated electrical characteristics of single-gated feedback field effect transistors (FBFETs) and the influence of channel length variation of the memory window characteristics through the 3D device simulation. The simulations were carried out for various channel lengths from 50 nm to 100 nm. The FBFETs exhibited zero SS(< 1 mV/dec) and a current Ion/Ioff ratio∼1.27×1010. In addition, the memory windows were 0.31 V for 50 nm-channel-length devices while no memory windows were observed for 100 nm-channel-length devices

참고문헌 (12)

  1. Scott E. Thompson, "Moore's law: the future of Si microelectronics", Materials Today, 9(6), pp.20~25 (2006), Elsevier BV[DOI]
  2. Ionescu, Adrian M., "Tunnel field-effect transistors as energy-efficient electronic switches", nature, 479(7373), pp.329~337 (2011)
  3. K. Gopalakrishnan, "Impact Ionization MOS (I-MOS)—Part I: Device and Circuit Simulations", IEEE Transactions on Electron Devices, 52(1), pp.69~76 (2005), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  4. Padilla, Alvaro, "Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages", Electron Devices Meeting, 2008. IEDM 2008. IEEE International (2008), IEEE
  5. Kim, Minsuk, "Steep switching characteristics of single-gated feedback field-effect transistors", Nanotechnology, 28(5), pp.055205~ (2016)
  6. El Dirani, H., "Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory", SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016 IEEE (2016), IEEE
  7. Jing Wan, "A systematic study of the sharp-switching Z2-FET device: From mechanism to modeling and compact memory applications", Solid-State Electronics, 90, pp.2~11 (2013), Elsevier BV[DOI]
  8. "Manual, ATLAS User’S. "Device simulation software"", Silvaco Int, ~ (2008)
  9. Woo Young Choi, "Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV", dec, 2007, pp.28(8), 743~745[DOI]
  10. Cho, Min Hee, "Thin-Body SOI Capacitorless DRAM Cell Design Optimization and Scaling", Doctor, pp.2012
  11. DIMITRIJEV, Sima, "Principle of Semiconductor Devices" (2012), Oxford University Press
  12. Yeung, Chun Wing, "Steep On", Off Transistors for Future Low Power Electronics, University of California, 2014

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