자체 보정 CDAC를 이용한 10비트 20MS/s 비동기 축차근사형 ADC
A 10-bit 20-MS/s Asynchronous SAR ADC using Self-calibrating CDAC
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초록
본 논문은 10비트 비동기 SAR ADC에 사용되는 CDAC의 선형성을 개선하기 위한 커패시터 자체 보정 기법을 제안한다. 제안된 커패시터 자체 보정 기법은 10비트 CDAC의 상위 5비트의 각각의 커패시터의 값이 하위 커패시터의 값들의 합과 같아지도록 수행된다. Behavioral 시뮬레이션의 결과에 의하면, CDAC의 커패시터의 최대 부정합 오류가 4%일 때, 제안한커패시터 자체 보정 기법은 DNL과 INL를 각각 –0.810/+0.194LSB와 –0.832/+0.832LSB에서 –0.235/+0.178LSB와 -0.227/+0.227LSB로 개선시킨다. 1.2V 공급전압과 110nm CMOS 공정을 이용하여 제작된 10비트 비동기 SAR ADC의 면적과 전력소모는 각각 0.205mm2와 1.25mW이다. 20MS/s의 샘플율과 96.13kHz 입력 주파수에 대해 제안한 10비트 비동기 SAR ADC의 측정된 ENOB는 9.194비트이다.
Abstract
A capacitor self-calibration is proposed to improve the linearity of the capacitor digital-to-analog converter (CDAC)for an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with 10-bit resolution. The proposed capacitor self-calibration is performed so that the value of each capacitor of the upper 5 bits of the 10-bitCDAC is equal to the sum of the values of the lower capacitors. According to the behavioral simulation results, theproposed capacitor self-calibration improves the performances of differential nonlinearity (DNL) and integral nonlinearity(INL) from –0.810/+0.194 LSBs and -0.832/+0.832 LSBs to -0.235/+0.178 LSBs and –0.227/+0.227 LSBs, respectively,when the maximum capacitor mismatch of the CDAC is 4%. The proposed 10-bit 20-MS/s asynchronous SAR ADC isimplemented using a 110-nm CMOS process with supply of 1.2 V. The area and power consumption of the proposedasynchronous SAR ADC are 0.205 mm2 and 1.25 mW, respectively. The proposed asynchronous SAR ADC with thecapacitor calibration has a effective number of bits (ENOBs) of 9.194 bits at a sampling rate of 20 MS/s about a 2.4-VPPdifferential analog input with a frequency of 96.13 kHz.
참고문헌 (8)
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