Partial-isolation LDMOS의 항복전압과 온저항 분석
Breakdown Voltage and On-resistance Analysis of Partial-isolation LDMOS
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
본 논문에서는 Partial isolation lateral double diffused metal oxide semiconductor(Pi-LDMOS)의 항복전압에 대해 시뮬레이션을 통해 분석하였다. 항복전압 변화는 Partial buried oxide(P-BOX)의 다양한 파라미터(길이, 두께, 위치)에 따라 조사되었고, 그 메커니즘에 대해 명기하였다. 또한 항복전압과 trade-off 관계에 있는 온저항의 변화를 P-BOX 파라미터 변화에 따라 분석하였고 Figure of merit(FOM)을 계산하여 비교하였다. 제안된 구조에서 Lbox=5μm, tbox=2μm, Lbc=2μm일 경우 138V의 가장 높은 항복전압을 나타내었고, Lbox=5μm, tbox=1.6μm, Lbc=2μm일 경우 가장 높은 FOM을 나타내었다. 이는 conventional LDMOS대비 항복전압은 123%, FOM은 3.89배 향상된 수치이다. 따라서 Pi-LDMOS는 높은 항복전압과 FOM을 가져 Power IC의 안정적인 동작범위 향상에 기여할 수 있다.
Abstract
In this paper, the breakdown voltage of Pi-LDMOS (Partial isolation lateral double diffused metal oxidesemiconductor) was analyzed by simulation. Breakdown voltage variation is investigated under various settings ofParial buied oxide(P-BOX) parameters(length, thickness, location) and their mechanism is specified. In addition,the change in on-resistance in the breakdown voltage and trade-off relationship was analyzed according to the changein the P-BOX parameter, and the Figure-of-merit(FOM) was calculated and compared. In proposed structure,Lbox=5 μm, tbox=2 μm, and Lbc=2 μm showed the highest breakdown voltage of 138V, and Lbox=5 μm, tbox=1.6μm, and Lbc=2 μm showed the highest FOM. Compared to conventional LDMOS, the breakdown voltage is 123%and FOM is 3.89 times improved. Therefore, Pi-LDMOS has a high breakdown voltage and FOM, which cancontribute to the improvement of the stable operating range of the Power IC.
참고문헌 (12)
- KrishnanNadar Savithry Nikhil, "Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors", IEEE Transactions on Electron Devices, 63(10), pp.4003~4010 (2016), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- KrishnanNadar Savithry Nikhil, "SOI-LDMOS Transistors With Optimized Partial n+ Buried Layer for Improved Performance in Power Amplifier Applications", IEEE Transactions on Electron Devices, 65(11), pp.4931~4937 (2018), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Myoung Jin Lee, "Partial SOI type isolation for improvement of DRAM cell transistor characteristics", IEEE Electron Device Letters, 26(5), pp.332~334 (2005), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Jin Hyo Park, "Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor", IEEE Transactions on Electron Devices, 69(12), pp.6710~6716 (2022), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Yue Hu, "Dimension Effect on Breakdown Voltage of Partial SOI LDMOS", IEEE Journal of the Electron Devices Society, 5(3), pp.157~163 (2017), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- A.A. Orouji, "A New Partial-SOI LDMOSFET With Modified Electric Field for Breakdown Voltage Improvement", IEEE Transactions on Device and Materials Reliability, 9(3), pp.449~453 (2009), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- S. E. Jamali Mahabadi, "A novel step buried oxide Partial SOI LDMOSFET with Triple Drift layer", 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies, pp.174~177 (2011)
- Hossein Elahipanah, "A 1300-V 0.34-Ωㆍcm2 Partial SOI LDMOSFET With Novel Dual Charge Accumulation Layers", IEEE Transactions on Electron Devices, 57(8), pp.1959~1965 (2010), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Garner DM, "The fabrication of a partial SOI substrate", Ninth International Symposium on Silicon-on-Insulator Technology and Devices, pp.73~78 (1999)
- Ali Houadef, "Design of an LDMOS Transistor Based on the 1 µm CMOS Process for High", Low Power Applications, 2022, pp.14(1), 17~[DOI]
- J. A. Appels, "High voltage thin layer devices (RESURF devices)", 1979 International Electron Devices Meeting, pp.238~241 (1979)
- Jiafei Yao, "SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions", IEEE Transactions on Electron Devices, 70(5), pp.2204~2209 (2023), Institute of Electrical and Electronics Engineers (IEEE)[DOI]