저전력 용량성 센서 인터페이스를 위한 저잡음 CMOS LDO 레귤레이터 설계
Design of the low noise CMOS LDO regulator for a low power capacitivesensor interface
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This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a 0.5 μm CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.
Abstract
This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a 0.5 μm CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.
참고문헌 (9)
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