패턴 기반 정렬을 활용한 고속-에너지 효율적인 컨볼루션 스파이킹 신경망 하드웨어 가속기의 모델 기반 동적 가지치기
High-Speed Energy-Efficient Model based Dynamic Pruning using Pattern-based Alignment for Convolutional Spiking Neural Network Hardware Accelerators
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Spiking neural network (SNN) is a structure that mimics biological neurons and processes through time-dependent signals called spikes. It resembles the functions of a biologꠓical brain, enabling energy-efficient and real-time processing. Despite being hardware-friendly, SNNs still require considerable computational resources. In this paper, we propose a Convolutional Spiking Neural Network (CSNN) architecture that leverages a preprocessed dataset for hardware accelerator-based pruning to reduce latency and power consumption. The dataset is encoded as binary data and preprocessed on the front-end by sorting it based on patterns. Once the dataset is input into the hardware accelerator, the system identifies data that does not require convolution operations. This allows the removal of inactive neurons at the Register Transfer Level (RTL). Since the neurons to be removed follow a similar pattern to the pruned neurons in the previous time step, the cost of removal is almost negligible. By pruning neurons dynamically for each input image, a more efficient, high-speed, low-power hardware accelerator can be achieved. The pattern-based dataset classification was implemented in Python, while the hardware accelerator was developed using Verilog and synthesized on an FPGA. This approach reduces power consumption by 80.02%, while also requiring 7.27% fewer gates and achieving a 90.1% improvement compared to traditional convolutional spiking neural networks and conventional CNNs. The accuracy reaches 90.56% and each input is calculated in 8955 clock cycles, which takes 0.53s for 60000 images in 100MHz board. This approach demonstrates the potential for enabling real-time learning on NPUs by integrating learning accelerators in future applications.
Abstract
Spiking neural network (SNN) is a structure that mimics biological neurons and processes through time-dependent signals called spikes. It resembles the functions of a biologꠓical brain, enabling energy-efficient and real-time processing. Despite being hardware-friendly, SNNs still require considerable computational resources. In this paper, we propose a Convolutional Spiking Neural Network (CSNN) architecture that leverages a preprocessed dataset for hardware accelerator-based pruning to reduce latency and power consumption. The dataset is encoded as binary data and preprocessed on the front-end by sorting it based on patterns. Once the dataset is input into the hardware accelerator, the system identifies data that does not require convolution operations. This allows the removal of inactive neurons at the Register Transfer Level (RTL). Since the neurons to be removed follow a similar pattern to the pruned neurons in the previous time step, the cost of removal is almost negligible. By pruning neurons dynamically for each input image, a more efficient, high-speed, low-power hardware accelerator can be achieved. The pattern-based dataset classification was implemented in Python, while the hardware accelerator was developed using Verilog and synthesized on an FPGA. This approach reduces power consumption by 80.02%, while also requiring 7.27% fewer gates and achieving a 90.1% improvement compared to traditional convolutional spiking neural networks and conventional CNNs. The accuracy reaches 90.56% and each input is calculated in 8955 clock cycles, which takes 0.53s for 60000 images in 100MHz board. This approach demonstrates the potential for enabling real-time learning on NPUs by integrating learning accelerators in future applications.
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