경량 딥러닝 가속기를 위한 희소 행렬 압축 기법 및 하드웨어 설계
Sparse Matrix Compression Technique and Hardware Design for Lightweight Deep Learning Accelerators
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
Deep learning models such as convolutional neural networks and recurrent neual networks process a huge amounts of data, so they require a lot of storage and consume a lot of time and power due to memory access. Recently, research is being conducted to reduce memory usage and access by compressing data using the feature that many of deep learning data are highly sparse and localized. In this paper, we propose a compression-decompression method of storing only the non-zero data and the location information of the non-zero data excluding zero data. In order to make the location information of non-zero data, the matrix data is divided into sections uniformly. And whether there is non-zero data in the corresponding section is indicated. In this case, section division is not executed only once, but repeatedly executed, and location information is stored in each step. Therefore, it can be properly compressed according to the ratio and distribution of zero data. In addition, we propose a hardware structure that enables compression and decompression without complex operations. It was designed and verified with Verilog, and it was confirmed that it can be used in hardware deep learning accelerators.
Abstract
Deep learning models such as convolutional neural networks and recurrent neual networks process a huge amounts of data, so they require a lot of storage and consume a lot of time and power due to memory access. Recently, research is being conducted to reduce memory usage and access by compressing data using the feature that many of deep learning data are highly sparse and localized. In this paper, we propose a compression-decompression method of storing only the non-zero data and the location information of the non-zero data excluding zero data. In order to make the location information of non-zero data, the matrix data is divided into sections uniformly. And whether there is non-zero data in the corresponding section is indicated. In this case, section division is not executed only once, but repeatedly executed, and location information is stored in each step. Therefore, it can be properly compressed according to the ratio and distribution of zero data. In addition, we propose a hardware structure that enables compression and decompression without complex operations. It was designed and verified with Verilog, and it was confirmed that it can be used in hardware deep learning accelerators.
참고문헌 (17)
- Lin, C. H., "A 3.4-to-13.3TOPS", W 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC, 2020 (2020), 134~136
- 안세현, "경량화된 딥러닝 구조를 이용한 실시간 초고해상도 영상 생성 기술", 방송공학회 논문지, 26(2), pp.167~174 (2021), 한국방송∙미디어공학회[DOI]
- 김진호, "딥러닝 신경망을 이용한 문자 및 단어 단위의 영문 차량 번호판 인식", (사)디지털산업정보학회 논문지, 16(4), pp.19~28 (2020), (사)디지털산업정보학회
- 장중봉, "채널 상태 정보를 이용한 딥 러닝 기반 실내 위치 확인 시스템", (사)디지털산업정보학회 논문지, 16(4), pp.1~7 (2020), (사)디지털산업정보학회
- 딥러닝 모델 경량화 기술 분석, "이경하", 발한국과학기술정보연구원, 89~ (2020)
- 오광일, "인공지능 뉴로모픽 반도체 기술 동향", 전자통신동향분석, 35(3), pp.76~84 (2020)
- Chen, Y., "A Survey of Accelerator Architectures for Deep Neural Networks", Engineering, 6, pp.264~274 (2020)
- 추연호, "딥러닝을 이용한 IOT 기기 인식 시스템", 반도체디스플레이기술학회지, 18(2), pp.1~5 (2019), 한국반도체디스플레이기술학회
- 김윤빈, "딥러닝을 활용한 IoT 센서 데이터 처리에 관한 연구", 석사, 컴퓨터정보학과, pp.2019
- 이용주, "경량 딥러닝 기술 동향", 전자통신동향분석, 34(2), pp.40~50 (2019)
- Han, S., "Deep compression : Compressing deep neural networks with pruning, trained quantization and huffman coding", International Conference on Learning Representations(ICLR), San Juan, Puerto Rico (2016)
- Zhu, M. H., "To prune, or not to prune: exploring the efficacy of pruning for model compression" (2018), International Conference on Learning Representations(ICLR)
- Kanellopoulos, K., "SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations", Proceedings of the 52nd Annual IEEE, 2019, 600~614
- Park, Y., "GRLC: Grid-based Run-length Compression for Energy-efficient CNN Accelerator", Proceedings of the ACM, 2020, 91~96
- Liu, W., "CSR5: An Efficient Storage Format for Cross-Platform Sparse Matrix-Vector Multiplication", Proceedings of the 29th ACM International Conference on Supercomputing (ICS '15), pp.339~350 (2015)
- M. Rhu, "Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks", IEEE International Symposium on High Performance Computer Architecture(HPCA), pp.78~91 (2018)
- "The University of Florida Sparse Matrix Collection"[URL]