GPNPU 아키텍처 설계 및 CNN을 이용한 성능 평가
GPNPU Architecture Design and its Performance Evaluation Using CNN
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초록
The deep neural networks (DNN) models are applied to diverse fields due to its astonishing performance. The DNN processing requires a huge number of computations with a massive amount of data. To expedite the DNN processing, AI accelerators are typically used. However, most of the proposed accelerator architectures are customized and tailored for a specific type of DNNs. This paper presents a GPNPU (General-Purpose Neural Processing Unit) architecture for efficiently processing various DNNs with instructions optimized for inference. The instructions go through different pipeline stages according to the instruction types. The pipeline stall is avoided with separate register files and corresponding datapath. The GPNPU was designed using Verilog-HDL and ported to UltraScale+ FPGA on ZCU102. It operates at 200 MHz with 0.444 W power consumption. Compared to the baseline, our GPNPU reduces the LUT and Flip-Flop usages by 15.6% and by 0.9%, respectively. Our GPNPU outperforms baseline in terms of execution time and power consumption at the same operating frequency. Additionally, Tiling allows GPNPU to process the convolution operation iteratively with reduced code size and data memory, consequently lowering power consumption. The output stationary dataflow enhances the energy efficiency via data reuse.
Abstract
The deep neural networks (DNN) models are applied to diverse fields due to its astonishing performance. The DNN processing requires a huge number of computations with a massive amount of data. To expedite the DNN processing, AI accelerators are typically used. However, most of the proposed accelerator architectures are customized and tailored for a specific type of DNNs. This paper presents a GPNPU (General-Purpose Neural Processing Unit) architecture for efficiently processing various DNNs with instructions optimized for inference. The instructions go through different pipeline stages according to the instruction types. The pipeline stall is avoided with separate register files and corresponding datapath. The GPNPU was designed using Verilog-HDL and ported to UltraScale+ FPGA on ZCU102. It operates at 200 MHz with 0.444 W power consumption. Compared to the baseline, our GPNPU reduces the LUT and Flip-Flop usages by 15.6% and by 0.9%, respectively. Our GPNPU outperforms baseline in terms of execution time and power consumption at the same operating frequency. Additionally, Tiling allows GPNPU to process the convolution operation iteratively with reduced code size and data memory, consequently lowering power consumption. The output stationary dataflow enhances the energy efficiency via data reuse.
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