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세트별 재사용 정보 기반 쓰래싱 저항 캐쉬 관리 기법

Reuse Information based Thrashing Resistant Cache Management Scheme

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참고문헌

키워드

주제분류컴퓨터학

초록

In recent computing systems, LRU replacement policy has been widely used because it can be simply implemented and applicable to most programs. However, if the working set size of the program is bigger than the actual cache size, LRU replacement policy may occur thrashing problem. Thrashing problem means that cache blocks are consistently replaced without re-referencing in the cache. This paper proposes a new cache management scheme to solve the thrashing problem in the second-level cache. The proposed scheme measures per set reuse frequency using EAF structure to find thrashing sets. When the cache miss occurs, it tests whether the address of the missed block is stored or not. If the address of the missed block is stored, it means that the recently evicted block is re-requested, so the reuse frequency is predicted high. In this case, the corresponding counter of the set is increased. When the counter value is bigger than the threshold value, we assume that the corresponding set shows high reuse frequency. The proposed scheme assigns the set with high reuse frequency to the additional small size cache to keep the blocks in the cache for a long time. Our experimental results show that the proposed scheme improves the IPC by 3.81% on average.

Abstract

In recent computing systems, LRU replacement policy has been widely used because it can be simply implemented and applicable to most programs. However, if the working set size of the program is bigger than the actual cache size, LRU replacement policy may occur thrashing problem. Thrashing problem means that cache blocks are consistently replaced without re-referencing in the cache. This paper proposes a new cache management scheme to solve the thrashing problem in the second-level cache. The proposed scheme measures per set reuse frequency using EAF structure to find thrashing sets. When the cache miss occurs, it tests whether the address of the missed block is stored or not. If the address of the missed block is stored, it means that the recently evicted block is re-requested, so the reuse frequency is predicted high. In this case, the corresponding counter of the set is increased. When the counter value is bigger than the threshold value, we assume that the corresponding set shows high reuse frequency. The proposed scheme assigns the set with high reuse frequency to the additional small size cache to keep the blocks in the cache for a long time. Our experimental results show that the proposed scheme improves the IPC by 3.81% on average.

참고문헌 (12)

  1. C. J. Wu, "SHiP: Signature-Based Hit Predictor for High Performance Caching", Proceedings of the International Symposium on Microarchitecture (MICRO), pp.430~441 (2011)
  2. G. S. Tyson, "A Modified approach to data cache management", Proceedings of the International Symposium on Microarchitecture (MICRO), pp.93~103 (1995)
  3. D. Rolán, "Adaptive Line Placement with the Set Balancing Cache", Proceedings of the International Symposium on Microarchitecture (MICRO), pp.529~540 (2009)
  4. J. Peir, "Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology", Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp.240~250 (1998)
  5. M. K. Qureshi, "The V-Way Cache: Demand Based Associativity via Global Replacement", Proceedings of International Symposium on Computer Architecture (ISCA), pp.544~555 (2005)
  6. 김재민, "Last Level Cache에서 캐시 실패율을 줄이기 위한 그룹 기반 교체 알고리즘", 한국차세대컴퓨팅학회 논문지, 6(5), pp.44~50 (2010), 한국차세대컴퓨팅학회
  7. 손동오, "재구성 가능한 라스트 레벨 캐쉬 구조를 위한 코어 인지 캐쉬 교체 기법", 한국컴퓨터정보학회논문지, 18(11), pp.1~12 (2013), 한국컴퓨터정보학회
  8. M. K. Qureshi, "Adaptive Insertion Policies for High Performance Caching", Proceedings of International Symposium on Computer Architecture (ISCA), pp.381~391 (2007)
  9. V. Seshadri, "The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing", Proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.355~366 (2012)
  10. B. H. Bloom, "Space", time Trade-offs in Hash Coding with Allowable Errors, 1970, 422~426
  11. T. Austin, "SimpleScalar: An Infrastructure for Computer System Modeling", Computer, 35(2), pp.59~67 (2002)
  12. "SPEC CPU2000 Benchmarks"[URL]

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