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차세대 모바일 메모리 기술의 정량적 비교 및 분석

Quantitative comparison and analysis of next generation mobile memory technologies

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참고문헌

키워드

주제분류컴퓨터학

초록

최근 모바일 디바이스에서 수행되는 응용 프로그램이 데이터-집약적으로 변화함에 따라, 모바일 메모리에 요구되는대역폭 및 소모되는 에너지가 증가하고 있으며 이를 개선하기 위한 여러 연구 및 기술 개발이 진행되고 있다. 그러나, 최신 모바일 메모리 기술 (LPDDR 혹은 Wide I/O) 시스템 측면 연구는 많이 이루어지지 않은 실정이다. 특히, 컴퓨터 시스템적인 측면에서 이러한 기술들의 정량적인 평가는 모바일 메모리 기술 개선에 매우 중요한 척도가될 수 있다. 본 논문에서는 현재 모바일 디바이스에서 사용되는 모바일 DRAM (Wide I/O and LPDDR3)을 채용한 컴퓨터 시스템을 시뮬레이션하고 이를 통해 얻은 결과를 바탕으로 차세대 모바일 DRAM의 에너지 효율 및 성능에 직접적인 영향을 주는 세부적인 요소를 정량적으로 분석하고 어느 부분이 개선점이 될 수 있는지를 보여준다.

Abstract

Recently, as mobile workloads are becoming more data-intensive, high data bandwidth is required for mobile memory which also consumes non-negligible system energy. A variety of researches and technologies are under development to improve and optimize mobile memory technologies. However, a comprehensive study on the latest mobile memory technologies (LPDDR or Wide I/O) has not been extensively performed yet. To construct high-performance and energy-efficient mobile memory systems, quantitative and detailed analysis of these technologies is crucial. In this paper, we simulate the computer system which adopts mobile DRAM technologies (Wide I/O and LPDDR3). Based on our detailed and comprehensive results, we analyze important factors that affect performance and energy-efficiency of mobile DRAM technologies and show which part can be improved to construct better systems.

참고문헌 (26)

  1. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, "Wide I", O Single Data Rate (Wide I, JEDEC STANDARD, pp.2011, ~
  2. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, "High Bandwidth Memory(HBM)DRAM", JEDEC STANDARD, ~ (2013)
  3. Krishna Kavi, "3D DRAM and PCMs in Processor Memory Hierarchy", Architecture of Computing Systems, LNCS, 8350, pp.183~195 (2014)
  4. Chiachen Chou, "CAMEO : A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache", Microarchitecture, 1(12), pp.1~12 (2014)
  5. Chang-Chi Lee, "An Overview of the Development of a GPU with integrated HBM on Silicon Interposer", Electronic Components and Technology Conference, pp.1439~1444 (2016)
  6. 전형규, "TSV를 활용한 3차원 구조 마이크로프로세서에서의 L2 캐쉬 접근 시간 향상률 분석", 한국차세대컴퓨팅학회 논문지, 8(4), pp.66~74 (2012), 한국차세대컴퓨팅학회
  7. Mohammand Hossein Hajkazemi, "Wide I", O or LPDDR? Exploration and Analysis of performance, Power and Temperture Trate-offs of Emerging DRAM Technologies in Enbedded MPSoCs, 2015, 62~69
  8. Mohammadsadegh Sadri, "Energy Optimization in 3D MPSoCs with Wide-I", O DRAM Using Temperature Variation Aware Bank-wise Refresh, 2014 (2014), 1~4
  9. Matthias Jung, "Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs", 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC), pp.1~6 (2014)
  10. Daniel W. Chang, "Dynamic Bandwidth Scaling for Embedded DSPs with 3D-Stacked DRAM and Wide I", Os, ACM International Conference on Computer-Aided Design (ICCAD), pp.2013 (2013)[DOI]
  11. Shibo Wang, "Reducing Data Movement Energy via Online Data Clustering and Encoding", MICRO 2016 49th Annual IEEE, 2016, 1~13
  12. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, "Double Data Rate(DDR)SDRAM", JEDEC STANDARD (2008)
  13. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, "DDR2 SDRAM SPECIFICATION", JEDEC STANDARD (2009)
  14. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, "DDR3 SDRAM Standard", JEDEC STANDARD (2012)
  15. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, "Low Power Double Data Rate(LPDDR)SDRAM Standard", JEDEC STANDARD (2010)
  16. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, "Low Power Double Data Rate 2(LPDDR2)", JEDEC STANDARD (2013)
  17. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, "Low Power Double Data Rate 3(LPDDR3)", JEDEC STANDARD (2015)
  18. M Ataul Karim, "Power Comparison of 2D, 3D and 2. 5D Interconnect Solutions and Power Optimization of Interposer Interconnects", Electronic Components and Technology Conference, pp.860~866 (2013)
  19. Marc Greenber, "LPDDR3 and Wide I", O DRAM : Interface Changes that give PC-Like Memory Performance to Mobile Devices, 2012, 1~37
  20. Keith Gutierrez, "PCB Design Guidelines for 0. 4mm Package-On-Package(PoP)Packages, Part I", TEXAS INSTRUMENTS, pp.1~25 (2009)
  21. F. Clermidy, "3D stacking for multi-core architectures : from WideIO to distributed caches", Circuits and Systems, 537(540), pp.537~540 (2013)
  22. Nathan Binkert, "The gem5 Simulator", ACM SIGARCH Computer Architecture News, 39(2), pp.1~7 (2011)
  23. Young Hoon Son, "Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations", International Symposium on Computer Architecture, pp.380~391 (2013)
  24. Jeffrey Stuecheli, "The Virtual Write Queue : Coordinating DRAM and Last-Level Cache Policies", International Symposium on Computer Architecture, pp.72~82 (2010)
  25. 김민중, "Energy Management of Server Systems for Data Centers Using Dynamic Voltage-Frequency Scaling", 한국차세대컴퓨팅학회 논문지, 8(3), pp.94~104 (2012), 한국차세대컴퓨팅학회
  26. 강동오, "저전력 서버 클러스터를 위한 모델 기반 자율 동적 전력 관리 기법", 한국차세대컴퓨팅학회 논문지, 10(3), pp.16~26 (2014), 한국차세대컴퓨팅학회

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