RISC-V 아키텍처 상에서의 쉐도우 스택 성능 평가 및 고찰
Performance Evaluation and Consideration of Shadow Stack on RISC-V Architecture
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RISC-V는 오픈소스 명령어 집합 아키텍처로, 다양한 하드웨어 구현에서 사용되며, RV64I 기본 명령어 집합과 16개의 표준 확장을 통해 시스템요구 사항에 맞게 유연하게 확장할 수 있다. 현재 RISC-V 아키텍처에서는 반환 주소를 보호하기 위해 쉐도우 스택 기법을 사용하고 있다. 본논문에서는 RISC-V 아키텍처에서 컴팩트 쉐도우 스택 메커니즘과 병렬 쉐도우 스택 메커니즘의 성능을 SPEC CPU 2017 및 beebs 벤치마크를사용하여 비교하였다. 실험 결과, 병렬 쉐도우 스택 메커니즘이 컴팩트 쉐도우 스택 메커니즘보다 더 높은 오버헤드를 보이는 것으로 나타났다. 이는 RISC-V 아키텍처의 한계로 인해 병렬 메커니즘의 효율성이 떨어짐을 시사하며, 따라서 컴팩트 쉐도우 스택이 RISC-V 아키텍처에 더 적합함을보여준다. 또한 본 논문에서 기존 RISC-V 쉐도우 스택의 보안상 한계를 파악하고, RISC-V의 안전한 수행 환경을 보장하기 위해 쉐도우 스택 메커니즘의 성능과 보안성을 향상시키는 방향을 제시한다.
Abstract
RISC-V is an open-source instruction set architecture, used in various hardware implementations, and can be flexibly expanded tomeet system requirements through the RV64I base instruction set and 16 standard extensions. Currently, the RISC-V architecture employsthe shadow stack technique to protect return addresses. This paper compares the performance of the compact shadow stack mechanismand the parallel shadow stack mechanism in the RISC-V architecture using the SPEC CPU 2017 and beebs benchmarks. Experimentalresults show that the parallel shadow stack mechanism exhibits higher overhead than the compact shadow stack mechanism. This suggeststhat the efficiency of the parallel mechanism is reduced due to the limitations of the RISC-V architecture, making the compact shadowstack more suitable for RISC-V. Additionally, this paper identifies the security limitations of the existing RISC-V shadow stack and proposesdirections for enhancing the performance and security of shadow stack mechanisms to ensure a secure execution environment for RISC-V.
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