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황화 암모늄을 이용한 Al2O3/HfO2 다층 게이트 절연막 트랜지스터 전기적 및 계면적 특성 향상 연구

Improvement of the carrier transport property and interfacial behavior in InGaAs quantum well Metal-Oxide-Semiconductor Field-Effect-Transistors with sulfur passivation

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초록

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In0.7Ga0.3As quantum-well (QW) metal-oxide semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In0.7Ga0.3As QW MOSFETs with and without (NH4)2S treatment and then deposited 1/4 nm of Al2O3/HfO2 through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density Dit (2.83×1012 cm-2eV-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

Abstract

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In0.7Ga0.3As quantum-well (QW) metal-oxide semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In0.7Ga0.3As QW MOSFETs with and without (NH4)2S treatment and then deposited 1/4 nm of Al2O3/HfO2 through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density Dit (2.83×1012 cm-2eV-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

참고문헌 (9)

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  3. C. B. Zota, "High Performance Quantum Well InGaAs-On-Si MOSFETs With sub-20 nm Gate Length For RF Applications", 2018 IEEE Int. Electron Devices Meet., pp.39.4.1~39.4.4 (2018)
  4. M. Yokoyama, "Sulfur cleaning for (100), (111)A, and (111)B InGaAs surfaces with In content of 0.53 and 0.70 and their Al2O3", InGaAs MOS interface properties, 2012 (2012), 167~170
  5. F. Xue, "Channel Thickness Dependence of InGaAs Quantum-Well Field-Effect Transistors With High-k Gate Dielectrics", IEEE Electron Device Lett, 33(9), pp.1255~1257 (2012)
  6. S. Guha, "Effects of gate-last and gate-first process on deep submicron inversion-mode InGaAs n-channel metal-oxide-semiconductor field effect transistors", J. Appl. Phys., 109(5), pp.053709(1)~053709(6) (2011)
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  8. J. -G. Kim, "Impact of in situ atomic layer deposition TiN", high-κ stack onto In 0. 53 Ga 0. 47 As MOSCAPs on 300 mm Si substrate, 2019, pp.58(4), 040905(1)~040905(4)
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