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저전력 10 Gbps CMOS 병렬-직렬 변환기

A low-power 10 Gbps CMOS parallel-to-serial converter

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초록

This paper presents a 10Gbps CMOS parallel-to-serial converter for transmission of sensor data. A low-noise clock multiplying unit(CMU) and a multiplexer with controllable data sequence are proposed. The transmitter was fabricated in 0.13 ᅠum CMOS process and the measured total output jitter was less than 0.1 ᅠUIpp(unit-interval, peak-to-peak) over 20 ᅠkHz to 80 ᅠMHz bandwidth. The jitter of the CMU output only was measured as 0.2 ᅠps,rms. The transmitter dissipatesless than 200 mW from 1.5 V/2.5 V power supplies.

Abstract

This paper presents a 10Gbps CMOS parallel-to-serial converter for transmission of sensor data. A low-noise clock multiplying unit(CMU) and a multiplexer with controllable data sequence are proposed. The transmitter was fabricated in 0.13 ᅠum CMOS process and the measured total output jitter was less than 0.1 ᅠUIpp(unit-interval, peak-to-peak) over 20 ᅠkHz to 80 ᅠMHz bandwidth. The jitter of the CMU output only was measured as 0.2 ᅠps,rms. The transmitter dissipatesless than 200 mW from 1.5 V/2.5 V power supplies.

참고문헌 (10)

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  3. J. Cao, "OC-192 transmitter and receiver in standard 0.18-um CMOS", IEEE J. Solid-State Circuits, 37(12), pp.1768~1780 (2002)
  4. L. Henrickson, "Low-power fully integrated 10-Gb", s SONET, IEEE J. Solid-State Circuits, pp.2003, 38(10)[DOI]
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  6. S. Byun, "A 10-Gb", s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector, 2006, pp.41(11), 2566~2576
  7. L. I. Andersson, "Silicon bipolar chipset for SONET", SDH 10 Gb, IEEE J. Solid-State Circuits, pp.1995, 30(3)[DOI]
  8. H. Cong, "A 10-Gb", s 16:1 multiplexer and 10-GHz Clock Synthesizer in 0.25-um SiGe BiCMOS, 2001, pp.36(12), 1946~1953
  9. B.Razavi, "Design of Integrated Circuits for Optical Communications" (2003), McGraw-Hill
  10. International Telecommunication Unit, "Recommendation: Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks", ~ (2004)

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