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WSN을 위한 128비트 확장된 데이터 블록을 갖는 고성능 HIGHT 설계

High Performance HIGHT Design with Extended 128-bit Data Block Length for WSN

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초록

This paper presents a high performance HIGHT processor that can be applicable for CCM mode. In fact, HIGHT algorithm is a 64-bit block cipher. However, the proposed HIGHT extends the basic block length to 128-bit. The proposed HIGHT is operated as 128-bit block cipher and it can treat 128-bit block at once. Thus, it can be applicable for the various WSN applications that need fast andultralight 128-bit block cipher, in particular, to be operated in CCM mode. In addition, the proposed HIGHT processor shares the commonlogics such as 128-bit key scheduler and control logics during encryption and decryption to reduce the area overhead caused bythe extension of data block length. From the simulation results, the circuit area and power consumption of the proposed HIGHT areincreases as 40% and 64% compared to the conventional 64-bit counterpart. However, the throughput of the proposed HIGHT can beup to two times as fast. Consequently, the proposed HIGHT is useful for USN and handheld devices based on battery as well as RFIDtag the size of circuit is less than 5,000 gates.

Abstract

This paper presents a high performance HIGHT processor that can be applicable for CCM mode. In fact, HIGHT algorithm is a 64-bit block cipher. However, the proposed HIGHT extends the basic block length to 128-bit. The proposed HIGHT is operated as 128-bit block cipher and it can treat 128-bit block at once. Thus, it can be applicable for the various WSN applications that need fast andultralight 128-bit block cipher, in particular, to be operated in CCM mode. In addition, the proposed HIGHT processor shares the commonlogics such as 128-bit key scheduler and control logics during encryption and decryption to reduce the area overhead caused bythe extension of data block length. From the simulation results, the circuit area and power consumption of the proposed HIGHT areincreases as 40% and 64% compared to the conventional 64-bit counterpart. However, the throughput of the proposed HIGHT can beup to two times as fast. Consequently, the proposed HIGHT is useful for USN and handheld devices based on battery as well as RFIDtag the size of circuit is less than 5,000 gates.

참고문헌 (7)

  1. L. Huai, "An Energy-Efficient AES-CCM Implementation for IEEE802. 15. 4 Wireless Sensor Networks", 2009 International Conf. on NetworksSecurity, Wireless Communications and Trusted Computing, pp.394~397 (2009)
  2. F. Bin, "Parallel and multiplex architecture of AES-CCM coprocessor Implementation for IEEE802. 15. 4 Wireless Sensor Networks", 2013 Fourth International Conf. on Emerging Intelligent Data and Web Technologies, pp.149~153 (2013)
  3. D. Whiting, "Counter with CBCMAC(CCM)", RFC 3610, ~ (2003)
  4. M. Feldhofer, "AES implementation on grain of sand", IEE Proc. Information Security, 152(1), pp.13~20 (2005)
  5. A. Satoh, "A compact rijndael hardware architecture with S-Box optimization", Proc. ASIACRYTP2001 LNCS, 2248, pp.239~254 (2001)
  6. D. Hong, "HIGHT : A new block cipher suitable for lowresource device", Proc. CHES2006 LNCS, 4249, pp.46~59 (2006)
  7. Y. I. Lim, "Implementation of HIGHT cryptic circuit for RFID tag", IEICE Electronic Express, 6(4), pp.180~186 (2009)

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