HIGHT 암복호화 병렬 실행을 위한 Key Scheduler 설계
Design of a Key Scheduler for Supporting the Parallel Encryption and Decryption Processes of HIGHT
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HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network thatneeds the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeyssimultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate thekeys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processesto minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times comparedto the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two timescompared to the conventional counterpart.
Abstract
HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network thatneeds the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeyssimultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate thekeys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processesto minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times comparedto the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two timescompared to the conventional counterpart.
참고문헌 (5)
- 서화정, "센서네트워크에 적용 가능한 HIGHT 알고리즘의 최적화 구현 기법", 한국정보통신학회논문지, 15(7), pp.1510~1516 (2011), 한국정보통신학회
- 백은태, "HIGHT 블록 암호 알고리즘의 고속화 구현", 정보보호학회논문지, 22(3), pp.495~504 (2012), 한국정보보호학회
- D. J. Hong, "HIGHT : a new block cipher suitable for low-resource device", Lecture Notes in Computer Science CHES 2006, 4249, pp.46~59 (2006)
- Y. I. Lim, "Implementation of HIGHT cryptic circuit for RFID tag", IEICE Electronics Express, 6(4), pp.180~186 (2009)
- J. H. Lee, "Parallel architecture for highspeed block cipher, HIGHT", Int’l Journal of Security and Its Applications, 8(2), pp.59~66 (2014)