Implementation of Lightweight Encryption Algorithm LEA
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This paper describes a hardware implementation of the lightweight block cipher algorithm LEA. The LEA crypto-processor designed in this paper supports three key lengths of 128, 192, and 256 bits. To achieve area-efficient and low-power implementation, both round block and key scheduler are optimized to share hardware resources used for encryption and decryption as well as for key scheduling. In addition, a parallel register structure with a novel key scheduling scheme is devised to reduce clock cycles for key scheduling, which results in an increase of performance by 20~30%. The LEA crypto-processor implemented with 21,000 gates was fabricated with a 0.18-um CMOS process. Test results show that all of the 22 chips tested functions correctly, resulting in 100% yield.
Abstract
This paper describes a hardware implementation of the lightweight block cipher algorithm LEA. The LEA crypto-processor designed in this paper supports three key lengths of 128, 192, and 256 bits. To achieve area-efficient and low-power implementation, both round block and key scheduler are optimized to share hardware resources used for encryption and decryption as well as for key scheduling. In addition, a parallel register structure with a novel key scheduling scheme is devised to reduce clock cycles for key scheduling, which results in an increase of performance by 20~30%. The LEA crypto-processor implemented with 21,000 gates was fabricated with a 0.18-um CMOS process. Test results show that all of the 22 chips tested functions correctly, resulting in 100% yield.
참고문헌 (13)
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