동종 접합 InGaAs 수직형 Fin TFET의 온도 의존 DC 특성에 대한 연구
Temperature-dependent DC Characteristics of Homojunction InGaAs vertical Fin TFETs
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field- Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating andthe high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthresholdswing of 80 mV/decade for drain voltage (VDS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, thesubthreshold swing at gate voltage (VGS) = threshold voltage (VT), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.
Abstract
In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field- Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating andthe high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthresholdswing of 80 mV/decade for drain voltage (VDS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, thesubthreshold swing at gate voltage (VGS) = threshold voltage (VT), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.
참고문헌 (20)
- A. M. Ionescu, "Tunnel field-effect transistors as energy-efficient electronic switches", Nature, 479(7373), pp.329~337 (2011)
- A. C. Seabaugh, "Low-voltage tunnel transistors for beyond CMOS logic", Proc. IEEE, 98(12), pp.2095~2110 (2010)
- F. Mayer, "Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance", 2008 IEEE Int. Electron Devices Meet, pp.1~5 (2008)
- A. Bowonder, "Low-voltage green transistor using ultra shallow junction and hetero-tunneling", Proc. IEEE Int. Workshop Junction Technol, pp.93~96 (2008)
- K. Bhuwalka, "Vertical tunnel field-effect transistor", IEEE Trans. Electron Devices, 51(2), pp.279~282 (2004)
- H. Lu, "Tunnel field-effect transistors : State-of-the-art", IEEE J. Electron Devices Soc, 2(4), pp.44~49 (2014)
- M. A. Khayer, "Drive currents and leakage currents in InSb and InAs nanowire and carbon nanotube band-to-band tunneling FETs", IEEE Electron Device. Lett, 30(12), pp.1257~1259 (2009)
- H. Schmid, "Fabrication of Vertical InAs-Si Heterojunction Tunnel Field Effect Transistors", 69th Device Res. Conf., pp.181~182 (2011)
- H. Riel, "InAs-Si Heterojunction Nanowire Tunnel Diodes and Tunnel FETs", 2012 IEEE Int. Electron Devices Meet, pp.16.6.1~16.6.4 (2012)
- K. Tomioka, "Tunnel field-effect transistor using InAs nanowire", Si heterojunction, 2011, pp.98, 083114(1)~083114(3)
- E. Memisevic, "Vertical Nanowire TFETs with Channel Diameter Down to 10 nm and Point S MIN of 35 mV", Decade, 2018, pp.39(7), 1089~1091
- E. Memisevic, "Individual Defects in InAs", InGaAsSb, decade, pp.Nano Lett, 2017[DOI]
- X. Zhao, "Sub-Thermal Subthreshold Characteristics in Top-Down InGaAs", InAs Heterojunction Vertical Nanowire Tunnel FETs, 2017, pp.38(7), 855~858
- A. Alian, "Record 47mV", dec top-down vertical nanowire InGaAs, 2018 VLSI Symp. Tech. Dig., pp.2018[DOI]
- M. Noguchi, "High Ion", Ioff and low subthreshold slope planar-type InGaAs tunnel field effect transistors with Zn-diffused source junctions, 2015, pp.118, 045712(1)~045712(15)
- X. Zhao, "InGaAs", InAs heterojunction vertical nanowire tunnel FETs fabricated by a top-down approach, 2014 (2014), 590~593
- J. -M. Baek, "Vertical InGaAs tunnel-field-effect transistors by an electro-plating fin formation technique", Solid-State Electron, 164, pp.107681(1)~107681(5) (2020)
- Q. Smets, "Calibration of Bulk Trap-Assisted Tunneling and Schokely-Read-Hall Currents and Impact on InGaAs Tunnel-FETs", IEEE Trans. Electron Devices, 64(9), pp.3622~3626 (2017)
- Y. Zhu, "Reliability Studies on High-Temperature Operation of Mixed As", Sb Staggered Gap Tunnel FET Material and Devices, 2014, pp.14(1), 245~254
- H. Zhao, "InGaAs Tunneling Field-Effect-Transistors With Atomic-Layer-Deposited Gate Oxides", IEEE Trans. Electron Devices, 58(9), pp.2990~2995 (2011)