A First-Order Noise-Shaping SAR ADC
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초록
This paper presents a first-order noise shaping successive approximation register (NS-SAR) ADC with a passive residue filter. To reduce circuit complexity and increase power efficiency, the proposed NS-SAR ADC architecture uses a first-order passive integrator based on charge sharing. The attenuation coming from the charge sharing is compensated by comparator gain and first-order noise shaping is achieved totally in a passive manner, which is less sensitive to PVT variation than conventional architectures using dynamic amplifiers. In a 65-nm CMOS process, the prototype occupies 0.013 mm2 area and consumes only 0.5 mW at sampling frequency of 150-MHz. The prototype achieves the maximum SNDR of 68 dB with oversampling ratio (OSR) of 4 and the peak value of 172.3 dB Schreier FoM (FoMS).
Abstract
This paper presents a first-order noise shaping successive approximation register (NS-SAR) ADC with a passive residue filter. To reduce circuit complexity and increase power efficiency, the proposed NS-SAR ADC architecture uses a first-order passive integrator based on charge sharing. The attenuation coming from the charge sharing is compensated by comparator gain and first-order noise shaping is achieved totally in a passive manner, which is less sensitive to PVT variation than conventional architectures using dynamic amplifiers. In a 65-nm CMOS process, the prototype occupies 0.013 mm2 area and consumes only 0.5 mW at sampling frequency of 150-MHz. The prototype achieves the maximum SNDR of 68 dB with oversampling ratio (OSR) of 4 and the peak value of 172.3 dB Schreier FoM (FoMS).
참고문헌 (12)
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