A 1.2V 30 MS/s SAR ADC with Foreground Capacitor Calibration
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– In this paper, a successive approximation register (SAR) ADC with foreground capacitor calibration is presented. In order to overcome the drawback of SAR architecture with low-power consumption, several techniques are adopted such as high-speed latch, three-stage comparator, reference-less architecture, custom metal-oxide-metal (MOM) capacitor, and foreground capacitor calibration. The design methodology and measurement procedure is presented in detail. The prototype ADC is fabricated in a 65 nm CMOS process, and it achieves signal-to-noise and distortion ratio (SNDR) over 60 dB at sampling frequency of 30 MS/s under 1.2 V supply voltage. The power consumption is 1.1 mW, and the chip area of the core ADC is 0.045 mm2.
Abstract
– In this paper, a successive approximation register (SAR) ADC with foreground capacitor calibration is presented. In order to overcome the drawback of SAR architecture with low-power consumption, several techniques are adopted such as high-speed latch, three-stage comparator, reference-less architecture, custom metal-oxide-metal (MOM) capacitor, and foreground capacitor calibration. The design methodology and measurement procedure is presented in detail. The prototype ADC is fabricated in a 65 nm CMOS process, and it achieves signal-to-noise and distortion ratio (SNDR) over 60 dB at sampling frequency of 30 MS/s under 1.2 V supply voltage. The power consumption is 1.1 mW, and the chip area of the core ADC is 0.045 mm2.
참고문헌 (10)
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