센서-회로 분리형 엑스선 DR 검출기를 위한 대면적CMOS 영상센서 모사 연구

Abstract

There are two methods to fabricate the readout electronic to a large-area CMOS imagesensor (LACIS). One is to design and manufacture the sensor part and signal processing electronicsin a single chip and the other is to integrate both parts with bump bonding or wire bonding aftermanufacturing both parts separately. The latter method has an advantage of the high yield becausethe optimized and specialized fabrication process can be chosen in designing and manufacturingeach part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication,is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as agate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiodestructure available in a standard CMOS process, Nphoto/Pepi type photodiode showed the highestquantum efficiency in the simulation study, though it requires one additional mask to control thedoping concentration of Nphoto layer. The optimized channel widths and lengths of 3 pixel transistorsare also determined by simulation. The select transistor is not significantly affected by channellength and width. But source follower transistor is strongly influenced by length and width. Inrow driver, to reduce signal time delay by high capacitance at output node, three stage inverterdrivers are used. And channel width of the inverter driver increases gradually in each step. Thesensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is appliedproper amount of pixel rows. It can help to reduce the long metal-line delay.