GPU-Based ECC Decode Unit for Efficient Massive Data Reception Acceleration
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In transmitting and receiving such a large amount of data, reliable data communication is crucial for normaloperation of a device and to prevent abnormal operations caused by errors. Therefore, in this paper, it is assumedthat an error correction code (ECC) that can detect and correct errors by itself is used in an environment wheremassive data is sequentially received. Because an embedded system has limited resources, such as a lowperformanceprocessor or a small memory, it requires efficient operation of applications. In this paper, wepropose using an accelerated ECC-decoding technique with a graphics processing unit (GPU) built into theembedded system when receiving a large amount of data. In the matrix–vector multiplication that forms theHamming code used as a function of the ECC operation, the matrix is expressed in compressed sparse row(CSR) format, and a sparse matrix–vector product is used. The multiplication operation is performed in thekernel of the GPU, and we also accelerate the Hamming code computation so that the ECC operation can beperformed in parallel. The proposed technique is implemented with CUDA on a GPU-embedded target board,NVIDIA Jetson TX2, and compared with execution time of the CPU.
Abstract
In transmitting and receiving such a large amount of data, reliable data communication is crucial for normaloperation of a device and to prevent abnormal operations caused by errors. Therefore, in this paper, it is assumedthat an error correction code (ECC) that can detect and correct errors by itself is used in an environment wheremassive data is sequentially received. Because an embedded system has limited resources, such as a lowperformanceprocessor or a small memory, it requires efficient operation of applications. In this paper, wepropose using an accelerated ECC-decoding technique with a graphics processing unit (GPU) built into theembedded system when receiving a large amount of data. In the matrix–vector multiplication that forms theHamming code used as a function of the ECC operation, the matrix is expressed in compressed sparse row(CSR) format, and a sparse matrix–vector product is used. The multiplication operation is performed in thekernel of the GPU, and we also accelerate the Hamming code computation so that the ECC operation can beperformed in parallel. The proposed technique is implemented with CUDA on a GPU-embedded target board,NVIDIA Jetson TX2, and compared with execution time of the CPU.
참고문헌 (32)
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