본문 바로가기
KERD
논문KCI 등재

고성능 저전력 하이브리드 L2 캐시 메모리를 위한 연관사상 집합 관리

Way-set Associative Managementfor Low Power Hybrid L2 Cache Memory

0

조회

0

다운로드

1

인용

0

참고문헌

키워드

초록

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

Abstract

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

참고문헌 (17)

  1. 박태진, "병렬 TLC STT-MRAM 기반 대용량 LLC 설계", 한국정보기술학회논문지, 15(12), pp.77~89 (2017), 한국정보기술학회[DOI]
  2. N.S. Kim, "Leakage Current: Moore's Law Meets Static Power", IEEE Computer Society, 36(12), pp.68~75 (2003)
  3. Y. Meng, "On the Limits of Leakage Power Reduction in Caches", Proceedings of High-Performance Computer Archutecture, pp.154~165 (2005)
  4. ITRS: International Technology Roadmap for Semiconductor, 2008 report, , ~
  5. K. Flautner, "Drowsy Cache: Simple Techniques for Reducing Leakage Power", Proceedings of Computer Archtecture, pp.148~157 (2002)
  6. Z. Hu, "Let Cache Decay: Reducing Leakage Energy via Exploitationi of Cache Generational Behavior", ACM Transactions on Computer Sytems, 20(2), pp.161~190 (2002)[DOI]
  7. J. Kin, "The Filter Cache: An Energy Efficient Memory Structure", Proceedings in ACM, 1997, 184~193
  8. 정보성, "저전력 집합연관 캐시를 위한 효과적인 알고리즘", 대한임베디드공학회논문지, 9(1), pp.25~32 (2014), 대한임베디드공학회[DOI]
  9. P.M. Palangappa, "WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory", IEEE Transactions on Computers, 64(4), pp.1028~1040 (2016)
  10. J.W. Ahn, "Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture", IEEE Transactions on Computers, 64(3), pp.940~951 (2015)
  11. S.P. Pack, "Future Cache Design Using STT-RAMs for Improved Energy Efficiency: Devices, Circuits and Architecture", Proceedings of Design Automation, pp.492~497 (2012)
  12. M. Imani, "Low Power Data-Aware STT-RAM based Hybrid Cache Architecture", Proceedings of Quality Electronic Design, pp.88~94 (2016)
  13. J. Li, "STT-RAM Based Energy-Efficiency Hybrid Cache for CMPs", Proceedings of VLSI and System-on-Chip, pp.31~36 (2011)
  14. A. Jadidi, "High-Endurance and Performance-Efficient Design of Hybrid Cache Architectures Through Adaptive Line Replacement", Proceedings of Low-Power Electronics and Design, pp.79~84 (2011)
  15. X. Wu, "Power and Performance of Read-Write Aware Hybrid Caches With Non-Volatile Memories", Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp.737~742 (2009)
  16. N. Muralimanohar, "CACTI 6.0: A tool to model large caches", pp.22~31 (2009)

관련 논문AI추천

이 간행물의 다른 논문 (6건)