MEMS 패키지용 Hollow Cu 관통비아의 형성공정
Formation of Hollow Cu Through-Vias for MEMS Packages
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초록
MEMS 패키징용 hollow Cu 비아의 형성거동을 분석하기 위해, 펄스-역펄스 전류밀도 및 도금시간에 따른 hollow Cu 비아의 미세구조를 관찰하고 평균 두께 및 두께 편차를 측정하였다. 펄스-역펄스 전류밀도를 -5 mA/㎠와 15 mA/㎠로 유지하며 3시간 도금시 hollow Cu 비아의 평균 도금두께는 5 μm이었으며 표준편차는 0.63 μm이었다. 도 금시간을 6시간으로 증가시 평균 도금두께는 10 μm, 표준편차는 1 μm로 균일한 두께의 hollow Cu 비아를 형성하는 것 이 가능하였다. 펄스-역펄스 전류밀도를 -10 mA/㎠와 30 mA/㎠ 이상으로 증가시킨 경우에는 도금시간 증가에 따라 도금두께보다 도금두께의 표준편차가 더 크게 증가하여 균일한 hollow Cu 비아의 형성이 어려웠다.
Abstract
In order to investigate the formation behavior of hollow Cu via for MEMS packaging, we observed the microstructure of the Cu vias and measured the average thickness and the thickness deviation with variations of pulsereverse pulse current density and electrodeposition time. With electrodeposition for 3 hours at the pulse and reverse pulse current densities of -5 mA/㎠ and 15 mA/㎠, the average thickness and the thickness deviation of the Cu vias were 5 μm and 0.63 μm, respectively. With increasing the electrodeposition time to 6 hours, it was possible to form the Cu vias, of which the average thickness and thickness variation of the Cu vias were 10 μm and 1 μm, respectively. With increasing the pulse and reverse pulse current densities to -10 mA/㎠ and 30 mA/㎠, Cu vias of uniform thickness could not be formed due to the faster increase of the thickness deviation than that of the average thickness with increasing the electrodeposition time.
참고문헌 (18)
- 박선희, "Cu 비아를 이용한 MEMS 센서의 스택 패키지용Interconnection 공정", 마이크로전자 및 패키징학회지, 14(4), pp.63~69 (2007), 한국마이크로전자및패키징학회
- 문종태, "Cu", Sn Rim 본딩을 이용한 MEMS 패키지의 Cap 형성공정, 2008, pp.15(4), 31~39[DOI]
- A. C. Imhoff, "Packaging technologies for RFICs : current status and future trends", 1999 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp.7~ (1999)
- H. Reichl, "Overview and development trends in the field of MEMS packaging", Proc. IEEE MEMS 2001 Conf., pp.1~5 (2001)
- C. Statter, "Design and fabrication of a miniature pressure sensor head using direct bonded ultrathin silicon wafers", J. Micromech. Microeng., 7, pp.108~110 (1996)
- T. Seki, "Low-loss RF MEMS metal-to-metal contact switch with CSP structure", Tech. Dig. 12th Int. Conf. Solid-state Sensors, Actuators and Microsystems, pp.340~341 (2003)
- M. Sakata, "Micromachined relay switch which utilizes single crystal silicon electrostatic actuator", Proc. 12th IEEE Int. Conf. MEMS, pp.21~24 (1999)
- R. M. Henderson, "Silicon-based micromachined packages for high-frequency application", IEEE Trans. Micro. Theory Tech., 47, pp.1563~1569 (1999)
- A. Margomenos, "Fabrication and accelerated hermeticity testing of and on-wafer package for RF MEMS", IEEE Trans. Micro. Theory Tech., 52, pp.1626~1636 (2004)
- Y. K. Park, "A novel lowloss wafer-level packaging of the RF-MEMS devices", Proc. 15th IEEE Int. Conf. MEMS, pp.681~681 (2002)
- U. Klein, "The advent of silicon microphones in high-volume applications", MST News (2001)
- Y. K. Park, "A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon", IEEE MEMS Conf., pp.73~ (2003)
- P. Arunasalam, "Process integration for through-silicon vias", J. Vac. Sci. Technol., B24, pp.1780~1784 (2006)
- C. Ryu, "Suppression of power", ground inductive impedance and simultaneous switching noise using silicon through-via in a 3-D stacked chip package, 2007, pp.17, 855~857
- K. W. Lee, "Electrical characteristics of the three-dimensional interconnection structure for the chip stack package with Cu through vias", J. Electron. Mater., 36, pp.123~128 (2007)
- W. P. Dow, "Evaluating the filling performance of a copper plating formula using a simple galvanostat method", J. Electrochem. Soc., 153, pp.C190~C194 (2006)
- T. Kobayashi, "Via-filling using electroplating for build-up PCBs", Electrochimica Acta, 47, pp.85~89 (2001)
- D. Varadarajan, "A tertiary current distribution model for the pulse plating of copper into high aspect ratio sub-0.25 μm trenches", J. Electrochem. Soc., 147, pp.3382~3392 (2000)