A Study on the Correlation Between Board Level Drop Test Experiment and Simulation
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초록
Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.
Abstract
Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.
참고문헌 (13)
- JEDEC Standard JESD22-B111, "Board Level Drop Test Method of Components for Handheld Electronic Products", ~ (2003)
- JEDEC Standard JESD22-200-BAA0, "Subassembly Mechanical Shock", ~ (2001)
- Luan, J.E., "Modal Analysis and Dynamic Responses of Board Level Drop Test", 5th EPTC Conference Proc, pp.233~243 (2003)
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- Luan, J.E., "Simulation using Implicit Transient Analysis with Input-G Method", 6th EPTC Conference Proc (2004)
- T. Y. Tee, "Novel numerical and experimental analysis of dynamic responses under board level drop test", Proc. EuroSime Conf (2004)
- Xie, D., "Solder Joint Behavior of Area Airray Ptkages in Board Level Drop for Handheld Devices", 53rd ECTC Conference Proc..R (2003)
- Tee TY, "Application of drop test simulation in electronic packaging", 4th ASEAN ANSYS Conference (2002), Singapore
- Tee TY, "Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact", Proceedings of the 54th ECTC Conference (2004)
- Chengalva, M., "Effect of Circuit Board Flexure on Flip Chips before Underfill", Proc. 50th Electronic Components and Technology Conference (2000), Las Vegas, NV, USA
- 임지연, "BGA Type 유·무연 솔더의 기계적 충격에 대한 보드레벨 신뢰성 평가", 마이크로전자 및 패키징학회지, 15(4), pp.77~86 (2008), 한국마이크로전자및패키징학회
- 하상옥, "OSP•ENIG 표면 처리된 기판과 Sn-3.0Ag-0.5Cu 솔더 접합부의 낙하충격 신뢰성 평가", 마이크로전자 및 패키징학회지, 16(1), pp.33~38 (2009), 한국마이크로전자및패키징학회