공정 단계에 따른 박형 Package-on-Package 상부 패키지의 Warpage 특성 분석
Warpage Characteristics Analysis for Top Packages of Thin Package-on-Packages with Progress of Their Process Steps
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초록
박형 package-on-package의 상부 패키지에 대하여 PCB 기판, 칩본딩 및 에폭시 몰딩과 같은 공정단계 진행에따른 warpage 특성을 분석하였다. 100 μm 두께의 박형 PCB 기판 자체에서 136~214 μm 범위의 warpage가 발생하였다. 이와 같은 PCB 기판에 40 μm 두께의 박형 Si 칩을 die attach film을 사용하여 실장한 시편은 PCB 기판의 warpage와 유사한 89~194 μm의 warpage를 나타내었으나, 플립칩 공정으로 Si 칩을 PCB 기판에 실장한 시편은 PCB 기판과 큰 차이를보이는 -199~691 μm의 warpage를 나타내었다. 에폭시 몰딩한 패키지의 경우에는 DAF 실장한 시편은 -79~202 μm, 플립칩 실장한 시편은 -117~159 μm의 warpage를 나타내었다.
Abstract
Warpage of top packages to form thin package-on-packages was measured with progress of their process stepssuch as PCB substrate itself, chip bonding, and epoxy molding. The 100 μm-thick PCB substrate exhibited a warpage of136~214 μm. The specimen formed by mounting a 40 μm-thick Si chip to such a PCB using a die attach film exhibited thewarpage of 89~194 μm, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chipbonding of a 40 μm-thick chip to such a PCB possessed the warpage of -199~691 μm, which was significantly differentfrom the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bondingexhibited warpages of -79~202 μm and -117~159 μm, respectively.
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