칩 실장공정에 따른 Package on Package(PoP)용 하부 패키지의 Warpage 특성
Warpage Characteristics of Bottom Packages for Package-on-Package(PoP)with Different Chip Mounting Processes
0
조회
0
다운로드
3
인용
0
참고문헌
키워드
초록
Package on Package(PoP)용 하부 패키지에 대해 플립칩 본딩으로 칩을 기판에 실장한 패키지와 die attach film(DAF)을 사용하여 칩을 기판에 접착한 패키지의 warpage 특성을 비교하였다. 플립칩 본딩으로 칩을 기판에 실장한패키지와 DAF를 사용하여 칩을 기판에 실장한 패키지는 솔더 리플로우 온도인 260oC에서 각기 57 μm와 -102 μm의warpage를 나타내었다. 상온에서 260oC 사이의 온도 범위에서 플립칩 실장한 패키지는 -27~60 μm 범위의 warpage를 나타내는 반면에, DAF 실장한 패키지는 -50~-153 μm 범위의 warpage를 나타내었다.
Abstract
The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of 260oC, the packages processed with flip chip bonding and DAF bonding exhibited warpages of 57 μm and -102 μm, respectively. At the temperature range between room temperature and 260oC,the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from -27 μm to 60 μm and from -50 μm to -153 μm, respectively.
참고문헌 (13)
- 김준범, "3차원 적층 패키지를 위한 Cu", Ni, Sn-Ag, pp.Cu 미세 범프 구조의 열처리에 따른 금속간 화합물 성장 거동 분석, 마이크로전자 및 패키징학회지[DOI]
- 조영학, "3D 적층 IC를 위한 웨이퍼 레벨 본딩 기술", 마이크로전자 및 패키징학회지, 20(1), pp.7~13 (2013), 한국마이크로전자및패키징학회[DOI]
- M. J. Yim, "Effects of Material Properties on PoP Top Package Warpage Behaviors", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 1071, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2010)
- M. Amagi, "A Study of Package Warpage for Package on Package (PoP)", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 226, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2010)
- N. Vijayaragavan, "Package on Package Warpage - Impact on Surface Mount Yields and Board Level Reliability", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 389, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008)
- M. J. Yim, "Ultra Thin Top Package using Compression Mold: Its Warpage Control", Proc. Proc. 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1141, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2011)
- J. Zhao, "Effects of Package Design on Top PoP Package Warpage", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1081, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008)
- K. Y. Lee, "Electrical Characteristics of the Three-Dimensional Interconnection Structure for the Chip Stack Package with Cu through Vias", J. Electron. Mater, 36, pp.123~ (2007)
- Y. K. Jee, "Zinc and Tin- Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package", J. Electron. Mater, 38, pp.685~ (2009)
- F. Carson, "Controlling Top Package Warpage for PoP Applications", Proc. 57th Electronic Components and Technology Conference (ECTC), Reno, 737, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2007)
- F. Liu, "Halogen-Free Mold Compound Development for Ultra-Thin Packages", Proc. 57th Electronic Components and Technology Conference (ECTC), Reno, 1051, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2007)
- 이봉희, "무아레 간섭계를 이용한 유연 솔더와 무연 솔더 실장 WB-PBGA 패키지의 열-기계적 변형 거동", 마이크로전자 및 패키징학회지, 17(3), pp.17~26 (2010), 한국마이크로전자및패키징학회
- "Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature JEDEC Standard JESD22-B112A", JEDEC Solid State Technology Association, Arlington, ~ (2009)
