박형 기판을 사용한 Package-on-Package용 상부 패키지와 하부 패키지의 Warpage 분석
Warpage Analysis for Top and Bottom Packages of Package-on-Package Processed with Thin Substrates
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초록
박형 package-on-package의 상부 패키지와 하부 패키지에 대하여 에폭시 몰딩 컴파운드(EMC)에 따른warpage 특성을 분석하였다. 또한 동일한 EMC로 몰딩한 패키지들의 warpage 편차를 측정하고 박형 상부 기판과 하부기판 자체의 warpage 편차를 측정함으로서, 박형 패키지에서 warpage 편차를 유발하는 원인을 분석하였다. 박형 기판을사용한 상부 및 하부 패키지에서는 기판 자체의 큰 warpage 편차에 기인하여 EMC의 물성이 패키지의 warpage에 미치는 영향을 규명하는 것이 어려웠다. EMC의 몰딩 면적이 13 mm×13 mm로 기판(14 mm×14 mm)의 대부분을 차지하는상부 패키지에서는 온도에 따른 warpage의 변화 거동이 유사하였다. 반면에 EMC의 몰딩 면적이 8 mm×8 mm인 하부패키지의 경우에는 (+) warpage와 (−) warpage가 한 시편에 모두 존재하는 복합적인 warpage 거동에 기인하여 동일한EMC로 몰딩한 패키지들에서도 상이한 온도-warpage 거동이 측정되었다.
Abstract
Warpage analysis has been performed for top and bottom packages of thin package-on-packages processed with different epoxy molding compounds (EMCs). Warpage deviation was measured for packages molded with the same EMCs and also the warpage deviations of top and bottom substrates themselves were characterized in order to identify the major factor causing the package warpage. For the top and bottom packages processed with thin substrates, the warpage deviation of the substrates was large, which made it difficult to figure out the effect of EMC properties on the package warpage. Top packages, where the molding area of 13 mm×13 mm covered the most of the substrate area (14 mm×14 mm), exhibited similar warpage behavior with changing the temperature. On the other hand, bottom packages, where the molding area was only 8 mm×8 mm, exhibited the complex warpage behavior due to simultaneous occurrence of (+) and (−) warpages on the same package. Accordingly, the bottom packages showed dissimilar temperature-warpage behavior even being processed with the same EMCs.
참고문헌 (20)
- J. L. Leila, "Numerical Analysis of Thermomechanical Reliability of Through Silicon Vias (TSVs) and Solder Interconnects in 3-dimensional Integrated Circuits", Microelectron. Eng, 87(2), pp.208~ (2010)
- 박동현, "공정 단계에 따른 박형 Package-on-Package 상부 패키지의 Warpage 특성 분석", 마이크로전자 및 패키징학회지, 20(2), pp.65~70 (2014), 한국마이크로전자및패키징학회[DOI]
- N. Vijayaragavan, "Package on Package Warpage - Impact on Surface Mount Yields and Board Level Reliability", Proc. 58th Electronic Components and Technology Conference (ECTC), pp.389~ (2008), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- H. Eslampour, "Low Cost Cu Column fcPoP Technology", Proc. 62nd Electronic Components and Technology Conference (ECTC), pp.871~ (2012), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- F. Roa, "Very Thin POP and SIP Packaging Approaches to Achieve Functionality Integration prior to TSV Implementation", Proc. 64th Electronic Components and Technology Conference (ECTC), pp.1656~ (2014), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- 김철규, "잔류응력으로 인한 패키지 기판 굽힘 변형량 예측", 마이크로전자 및 패키징학회지, 20(1), pp.21~26 (2013), 한국마이크로전자및패키징학회[DOI]
- J. Zhao, "Effects of Package Design on Top PoP Package Warpage", Proc. 58th Electronic Components and Technology Conference (ECTC), pp.1081~ (2008), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- C. H. Chien, "Influences of the Moisture Absorption on PBGA Package’s Warpage during IR Reflow Process", Microelectron. Reliab, 43(1), pp.131~ (2003)
- G. Kelly, "The Importance of Molding Compound Chemical Shrinkage in the Stress and Warpage Analysis of PQFPs", Proc. 45th Electronic Components and Technology Conference (ECTC), pp.296~ (1996), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- M. J. Yim, "Ultra Thin Top Package using Compression Mold: Its Warpage Control", Proc. 61st Electronic Components and Technology Conference (ECTC), pp.1141~ (2011), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- W. D. van Driel, "Prediction and verification of process-induced warpage of electronic packages", Microelectron. Reliab, 43(5), pp.765~ (2003)
- C. Chiu, "Challenges of Thin Core Substrate Flip Chip Package on Advanced Si Nodes", Proc. 57th Electronic Components and Technology Conference (ECTC), pp.22~ (2007), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- 이봉희, "무아레 간섭계를 이용한 유연 솔더와 무연 솔더 실장 WB-PBGA 패키지의 열-기계적 변형 거동", 마이크로전자 및 패키징학회지, 17(3), pp.17~26 (2010), 한국마이크로전자및패키징학회
- "JEDEC Standard JESD22-B112A, Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature", JEDEC Solid State Technology Association, ~ (2009)
- M. J. Yim, "Effects of Material Properties on PoP Top Package Warpage Behaviors", Proc. 60th Electronic Components and Technology Conference (ECTC), pp.107~ (2010), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- S. Michaelides, "Die Cracking and Reliable Die Design for Flip-Chip Assemblies", IEEE Transactions on Advanced Packaging, 22(4), pp.602~ (1999)
- Y. Sawada, "Study of Package Warpage Behavior for High-Performance Flip-Chip BGA", Microelectron. Reliab, 43(3), pp.465~ (2003)
- N. Boyard, "Behaviour of a Moulded Composite Part: Modelling of Dilatometric Curve (Constant Pressure) or Pressure (Constant Volume) with Temperature and Conversion Degree Gradients", Composite Sci. Technol, 67(6), pp.943~ (2007)
- S. Y. Yang, "Solder Reflow Process Induced Residual Warpage Measurement and Its Influence on Reliability of Flip-Chip Electronic Packages", Microelectron. Reliab, 46(2), pp.512~ (2006)
- S. H. Cho, "New Dummy Design and Stiffener on Warpage Reduction in Ball Grid Array Printed Circuit Board", Microelectron. Reliab, 50(2), pp.242~ (2010)