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TSV 기반 3차원 소자의 열적-기계적 신뢰성

Thermo-Mechanical Reliability of TSV based 3D-IC

김택수|윤태식
한국마이크로전자및패키징학회 (The Microelectronics And Packaging Society)|2017.03|마이크로전자 및 패키징학회지 (Jornal of the Microelectronics and Packaging Society)|제24권 제1호|pp. 35-43

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참고문헌

키워드

ReliabilityFractureThermal conductivityThrough-Silicon-ViaCoefficient of Thermal Expansion
주제분류재료공학

초록

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

Abstract

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

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관련 논문AI추천

3차원 패키징용 TSV의 열응력에 대한 열적 전기적 특성기세호, 정일호, 정재필한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2014 · 제20권 제2호Though-silicon-via를 사용한 3차원 적층 반도체 패키징에서의 열응력에 관한 연구김병준, 이호영, 정성엽, 주영창, 황성환한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2010 · 제17권 제1호수치해석에 의한 TSV 구조의 열응력 및 구리 Protrusion 연구이미경, 정훈선, 좌성훈한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2013 · 제20권 제2호3차원 적층 반도체에서의 열관리김성동한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2015 · 제22권 제2호3D IC 열관리를 위한 TSV Liquid Cooling System김성동, 김은경, 박만석한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2013 · 제20권 제3호열응력에 의한 실리콘 인터포저 위 금속 패드의 박락 현상김구성, 김보연, 김준모, 김택수, 정청하한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2022 · 제29권 제3호

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