수치해석에 의한 TSV 구조의 열응력 및 구리 Protrusion 연구
Numerical Analysis of Thermo-mechanical Stress and Cu Protrusion of Through-Silicon Via Structure
0
조회
0
다운로드
1
인용
0
참고문헌
키워드
초록
Through-Silicon Via (TSV) 기술은 3차원 적층 패키징를 위한 핵심 기술로서 큰 관심을 받고 있다. 그러나TSV 기술은 아직 다양한 공정상의 문제와 신뢰성 문제를 해결해야 하는 난제가 남아 있다. 특히 구리 비아(via)와 실리콘 기판의 큰 열팽창계수의 차이로 인한 열응력은 계면 박리, 크랙 발생, 구리 protrusion 등 다양한 신뢰성 문제를 발생시킨다. 본 연구에서는 구리 TSV 구조의 열응력을 수치해석을 이용하여 분석하였으며, 3차원 TSV 비아와 실리콘 기판의 응력 및 변형을 해석하였다. 비아의 크기, 비아와 비아 사이의 간격 및 비아의 밀도가 TSV 구조의 응력에 미치는 영향을 분석하였으며, 또한 어닐링(annealing) 온도 및 비아의 크기가 구리 protrusion에 미치는 영향을 관찰하였다. 구리TSV 구조의 신뢰성을 향상시키기 위해서는 적절한 비아와 비아 사이의 간격을 유지한 상태에서, 비아의 크기 및 비아의밀도는 작아야 한다. 또한 구리 protrusion을 감소시키기 위해서는 비아의 크기 및 어닐링 공정과 같은 공정의 온도를 낮추어야 한다. 본 연구의 결과는 TSV 구조의 열응력과 관련된 신뢰성 이슈를 이해하고, TSV 구조의 설계 가이드라인을제공하는데 도움을 줄 수 있을 것으로 판단된다.
Abstract
The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.
참고문헌 (22)
- 윤민승, "TSV (Through Silicon Via) 기술 동향", 마이크로전자 및 패키징학회지, 16(1), pp.1~6 (2009), 한국마이크로전자및패키징학회
- John H. Lau, "Evolution, Challenge, and Outlook of TSV, 3D IC Integration and 3D Silicon Integration", International Symposium on Advanced Packaging Materials, pp.462~488 (2011)
- K. N. Tu, "Reliability Challenges in 3D IC Packaging Technology", Microelectronics Reliability, 51, pp.517~ (2011)
- C. S. Selvanayagam, "Nonlinear Thermal Stress", Strain Analyses of Copper Filled TSV(Through Silicon Via) and their Flip-Chip Microbumps, 2008, 1073~1081
- 황성환, "Though-silicon-via를 사용한 3차원 적층 반도체 패키징에서의 열응력에 관한 연구", 마이크로전자 및 패키징학회지, 17(1), pp.69~73 (2010), 한국마이크로전자및패키징학회
- S. K. Ryu, "Characterization of Thermal Stresses in Through-Silicon Vias by Bending Beam Technique", Appl. Phys. Lett., 100(4), pp.041901~041904 (2012)
- J.-S. Yang, "TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization", Proc. ACM Design Automation Conf, pp.803~806 (2010)
- S. E. Thompson, "A 90-nm Logic Technology Featuring Strained Silicon", IEEE Trans. on Electron Devices, 51(11), pp.1790~ (2004)
- K. H. Lu, "Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias", Electronic Components and Technology Conference, pp.630~634 (2009)
- S.-K. Ryu, "Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration", IEEE Transactions on Device and Materials Reliability, 12, pp.255~262 (2012)
- F. X. Che, "Study on Cu Protrusion of Through-Silicon Via", IEEE Transactions on Components, Packaging and Manufacturing Technology, 3, pp.732~ (2013)
- T. Jiang, "Measurement and Analysis of Thermal Stresses in 3D Integrated Structures Containing Through-silicon-vias", Microelectronics Reliability, 53, pp.53~ (2013)
- I. De Wolf, "Cu pumping in TSVs: Effect of pre-CMP thermal budget", Microelectronics Reliability, 51, pp.1856~ (2011)
- M.C. Hsieh, "Thermo-mechanical Simulations For 4-Layer Stacked IC Packages", International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems, pp.1~7 (2008)
- P. Ramm, "Through Silicon Via Technology – Processes and Reliability for Wafer-Level 3D System Integration", Electronic Components and Technology Conference, pp.841~846 (2008)
- Xi Liu, "Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV)", Electronic Components and Technology Conference, pp.624~629 (2009)
- K.H. Lu, "Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects", IEEE ECTC Conference, pp.40~45 (2010)
- J. Zhang, "Modeling Thermal Stresses in 3-D IC Interwafer Interconnects", IEEE Transactions on Semiconductor Manufacturing, 19(4), pp.437~ (2006)
- Y. Xiang, "The Mechanical Properties of Electroplated Cu Thin Films Measured by means of the Bulge Test Technique", Proc. Mat. Res. Soc. Symp, 695, pp.L4.9.1~ (2002)
- M. Gad-del-Hak, "MEMS Handbook", pp.3~21 (2002), CRC press
- A. Heryanto, "Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication", Journal of Electronic Materials, 41(9), pp.2533~ (2012)
- L. Kong, "3D-interconnect: Visualization of Extrusion and Voids Induced in Copper-Filled Through-Silicon Vias (TSVs) at Various Temperatures using X-ray Microscopy", Microelectronic Engineering, 92, pp.24~ (2012)