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FE-SEM Image Analysis of Junction Interface of Cu Direct Bonding for Semiconductor 3D Chip Stacking

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주제분류기계공학

초록

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 °C, 150 °C, 200 °C, 350 °C and the pressure of 2303 N/cm2 and 3087 N/cm2. At 2303 N/cm2, the good bonding of copper substrate was confirmed at 350 °C, and at the increased pressure of 3087 N/cm2, the bonding condition of Cu was confirmed at low temperature junction temperature of 200 °C. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm2 and diffusion of Cu atoms at high temperature of 350 °C, which can lead to degradation in semiconductor manufacturing.

Abstract

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 °C, 150 °C, 200 °C, 350 °C and the pressure of 2303 N/cm2 and 3087 N/cm2. At 2303 N/cm2, the good bonding of copper substrate was confirmed at 350 °C, and at the increased pressure of 3087 N/cm2, the bonding condition of Cu was confirmed at low temperature junction temperature of 200 °C. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm2 and diffusion of Cu atoms at high temperature of 350 °C, which can lead to degradation in semiconductor manufacturing.

참고문헌 (13)

  1. P. Arunasalam, "Micro-fabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks", J. Vac. Sci. Technol, B24, pp.1780~ (2006)
  2. C. Ryu, "Suppression of power", ground inductive impedance and simultaneous switching noise using silicon through-via in a 3D stacked chip package, 2007, pp.17, 855~
  3. G. Giao, "Chip wafer hybrid bonding with Cu interconnect: high volume manufacturing process compatibility study", Proceeding of the international wafer-level packaging conference (2019)
  4. S. E. Kim, "Wafer level Cu-Cu directing bonding for 3D integration", Micro. Eng, 1, pp.1~6 (2015)
  5. D. R. Frear, "The mechanics of solder alloy interconnects" (1994), Van Nostrand Rein-hold
  6. 김광섭, "열가압 접합 공정으로 제조된 Cu-Cu 접합의 계면 접합 특성 평가", 대한기계학회논문집 A, 34(7), pp.929~933 (2010), 대한기계학회
  7. 강성근, "Fabrication and Challenges of Cu-to-Cu Wafer Bonding", 마이크로전자 및 패키징학회지, 19(2), pp.29~33 (2012), 한국마이크로전자및패키징학회[DOI]
  8. 김재원, "Cu 두께에 따른 Cu-Cu 열 압착 웨이퍼 접합부의 접합 특성 평가", 마이크로전자 및 패키징학회지, 17(4), pp.61~66 (2010), 한국마이크로전자및패키징학회
  9. Byung-Suk Lee, "고전력 반도체 모듈 적용을 위한 마이크로 입자 구리 소결 접합부의 미세조직 및 기계적 강도에 미치는 소결 접합 조건의 영향", 대한용접접합학회지, 37(2), pp.26~34 (2019), 대한용접접합학회[DOI]
  10. I. Radu, "Recent developments of Cu-Cu non-thermo compression bonding for wafer to wafer 3D stacking", Ieee International 3D Systems Integration Conference (3DIC), pp.1~6 (2010)
  11. Y. S. Tang, "Wafer level Cu-Cu bonding thchnology", Microelectronics Reliability, 52(2), pp.312~320 (2012)
  12. A. K. Panigrahi, "Low temperature Cu-Cu bonding technology in 3D integration : an extensive review", Journal of Electronic packaging, 140, pp.1~ (2017)
  13. A. Agrawal, "Diamond bit cutting for processing high topography wafers", Electronic packaging technology conference (2009)

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