A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS
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초록
In this paper, we present a study on a neural network operator that performs low resolution, low power, and high efficiency convolution operations in analog domains. The proposed operator is consisted of multiplying DAC (MDAC) with integrator structure and successive-approximation ADC (SAR ADC). The memory access frequency is lower than that of the digital operation because the addition operation is performed while the multiplication operation is performed, and the information is stored in the form of charge on the opamp output terminal. A digital-input, digital-output calculator consisting of MDAC and ADC was designed using a 65nm CMOS process. The result of transistor-level simulation was 30.11uW of power at 33.3MHz, which is equivalent to 2.21TOPS/W. And it shows improved power efficiency than conventional digital convolution operator.
Abstract
In this paper, we present a study on a neural network operator that performs low resolution, low power, and high efficiency convolution operations in analog domains. The proposed operator is consisted of multiplying DAC (MDAC) with integrator structure and successive-approximation ADC (SAR ADC). The memory access frequency is lower than that of the digital operation because the addition operation is performed while the multiplication operation is performed, and the information is stored in the form of charge on the opamp output terminal. A digital-input, digital-output calculator consisting of MDAC and ADC was designed using a 65nm CMOS process. The result of transistor-level simulation was 30.11uW of power at 33.3MHz, which is equivalent to 2.21TOPS/W. And it shows improved power efficiency than conventional digital convolution operator.
참고문헌 (16)
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