A hardware implementation of public-key cryptographic processor for 233-bit elliptic curve over binary field
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초록
This paper describes a design of 233-bit elliptic curve cryptography (ECC) processor that supports the NIST B-233 elliptic curve over binary field. The ECC-B233 processor computes point addition and point doubling operations on elliptic curve as well as scalar multiplication, which are required for ECC. It adopts the modified Montgomery ladder algorithm for scalar multiplication in order to make it strong against simple power analysis attacks. The finite field multiplication, squaring, and division operations over were implemented using shift-and-add serial multiplication and the extended Euclidian algorithm to achieve area-efficient implementation. A prototype chip for the ECC-B233 processor with 51,900 gates was fabricated using a 0.35-um CMOS process. Chip test results show that the ECC-B233 processor can operate with an operating clock up to 55 MHz. The ECC-B233 processor consumes 490,700 clock cycles for a scalar multiplication, which means that it takes about 9 msec at 55 MHz clock frequency. Forty-two chips out of 48 test chips were working correctly, resulting in the yield of 87%.
Abstract
This paper describes a design of 233-bit elliptic curve cryptography (ECC) processor that supports the NIST B-233 elliptic curve over binary field. The ECC-B233 processor computes point addition and point doubling operations on elliptic curve as well as scalar multiplication, which are required for ECC. It adopts the modified Montgomery ladder algorithm for scalar multiplication in order to make it strong against simple power analysis attacks. The finite field multiplication, squaring, and division operations over were implemented using shift-and-add serial multiplication and the extended Euclidian algorithm to achieve area-efficient implementation. A prototype chip for the ECC-B233 processor with 51,900 gates was fabricated using a 0.35-um CMOS process. Chip test results show that the ECC-B233 processor can operate with an operating clock up to 55 MHz. The ECC-B233 processor consumes 490,700 clock cycles for a scalar multiplication, which means that it takes about 9 msec at 55 MHz clock frequency. Forty-two chips out of 48 test chips were working correctly, resulting in the yield of 87%.
참고문헌 (13)
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