GF(2 ^{m} )상의 NIST 타원곡선을 지원하는 ECC 프로세서의 경량 하드웨어 구현
A Lightweight Hardware Implementation of ECC Processor Supporting NIST Elliptic Curves over GF(2 ^{m} )
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초록
NIST 표준으로 정의된 GF(2 ^{m} )상의 슈도 랜덤 곡선과 Koblitz 곡선을 지원하는 타원곡선 암호(ECC) 프로세서 설계에 대해 기술한다. 고정된 크기의 데이터 패스를 사용하여 5가지 키 길이를 지원함과 아울러 경량 하드웨어 구현을 위해 워드 기반 몽고메리 곱셈기를 기반으로 유한체 연산회로를 설계하였다. 또한, Lopez-Dahab 좌표계를 사용함으로써 유한체 나눗셈을 제거하였다. 설계된 ECC 프로세서를 FPGA 검증 플랫폼에 구현하고, ECDH(Elliptic Curve Diffie-Hellman) 키 교환 프로토콜 동작을 통해 하드웨어 동작을 검증하였다. 180-nm CMOS 표준 셀 라이브러리로 합성한 결과 10,674 등가 게이트와 9kbit의 dual-port RAM으로 구현되었으며, 최대 동작 주파수는 154 MHz로 평가되었다. 223-비트 슈도 랜덤 타원곡선 상의스칼라 곱셈 연산에 1,112,221 클록 사이클이 소요되며, 32.3 kbps의 처리량을 갖는다.
Abstract
A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitzcurves over defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on aword-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well asto achieve a lightweight hardware implementation. In addition, Lopez-Dahab’s coordinate system was adopted to removethe finite field division operation. The ECC processor was implemented in the FPGA verification platform and thehardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECCprocessor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-portRAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation overthe 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.
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