esign of Hybrid Finite Field Multiplier over GF(2^163) for Elliptic Curve Cryptosystems
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The multiplication over finite field GF(2^163) is the main arithmetic operation in Elliptic Curve Cryptography (ECC). Therefore, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a hardware implementation of hybrid multiplier over GF(2^163) is presented. The proposed multiplier operates in polynomial basis of GF(2^163). This multiplier’s size of 163 bits is currently recommended by the National Institute of Standards and Technology (NIST) in their elliptic curve digital signature standard (ECDSS), and is used in practice for binary field multiplication in elliptic curve cryptography. The hybrid architecture is -times faster than bit-serial architectures but with lower area complexity than bit-parallel ones, where the value for , 2≤t≤[m/2] , can be arbitrarily selected by the designer to set the tradeoff between area and speed. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved. This makes the proposed multipliers suitable for applications where the value of is large but space is of concern, e.g., resource constrained cryptographic systems such as smart cards and mobile phones. In addition, the proposed architecture is highly regular, simple, expandable and therefore, well-suited for VLSI implementation.
Abstract
The multiplication over finite field GF(2^163) is the main arithmetic operation in Elliptic Curve Cryptography (ECC). Therefore, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a hardware implementation of hybrid multiplier over GF(2^163) is presented. The proposed multiplier operates in polynomial basis of GF(2^163). This multiplier’s size of 163 bits is currently recommended by the National Institute of Standards and Technology (NIST) in their elliptic curve digital signature standard (ECDSS), and is used in practice for binary field multiplication in elliptic curve cryptography. The hybrid architecture is -times faster than bit-serial architectures but with lower area complexity than bit-parallel ones, where the value for , 2≤t≤[m/2] , can be arbitrarily selected by the designer to set the tradeoff between area and speed. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved. This makes the proposed multipliers suitable for applications where the value of is large but space is of concern, e.g., resource constrained cryptographic systems such as smart cards and mobile phones. In addition, the proposed architecture is highly regular, simple, expandable and therefore, well-suited for VLSI implementation.
참고문헌 (11)
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