Reverse Engineering for Xilinx FPGA Chips using ISE Design Tools
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초록
SRAM-based Field Programmable Gate Arrays (FPGAs) are more widely used compared to Flash-based and anti-fuse based FPGAs in various industries. One disadvantage of the SRAM-based FPGA is that SRAM is natively volatile and thus it requires additional nonvolatile memory to store the netlist information of the circuit outside the FPGA. When the FPGA is powered on, the bitstream file is transferred from the external nonvolatile memory to the SRAM-based FPGA. The secure issues arise if the bitstream is modified or corrupted by attacker resulting in a fatal problem in the circuit. Therefore, reverse engineering that converting a bitstream into an internal netlist is necessary to find such harmful modification. In this paper, we describe the overall process of reverse engineering based on ISE design tools in details. According to the experimental results, the proposed reverse engineering tool can recover 88% internal circuit as for the example of 64-bit LFSR design.
Abstract
SRAM-based Field Programmable Gate Arrays (FPGAs) are more widely used compared to Flash-based and anti-fuse based FPGAs in various industries. One disadvantage of the SRAM-based FPGA is that SRAM is natively volatile and thus it requires additional nonvolatile memory to store the netlist information of the circuit outside the FPGA. When the FPGA is powered on, the bitstream file is transferred from the external nonvolatile memory to the SRAM-based FPGA. The secure issues arise if the bitstream is modified or corrupted by attacker resulting in a fatal problem in the circuit. Therefore, reverse engineering that converting a bitstream into an internal netlist is necessary to find such harmful modification. In this paper, we describe the overall process of reverse engineering based on ISE design tools in details. According to the experimental results, the proposed reverse engineering tool can recover 88% internal circuit as for the example of 64-bit LFSR design.
참고문헌 (13)
- H. Yu, "Recent Advances in FPGA Reverse Engineering", Electronics, 7(10) (2018)
- M. Wirthlin, "High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond", Proceedings of the IEEE, 103(3), pp.379~389 (2015)
- J. -B. Note, "From the bitstream to the netlist", Proc. 16th Int. ACM, 2008, pp.8, 264~264
- F. Benz, "Bil: A tool-chain for bitstream reverse-engineering", 22th International Conference on Field Programmable Logic and Applications (FPL), pp.735~738 (2012)
- Z. Ding, "Deriving an NCD file from an FPGA bitstream : Methodology, architecture and evaluation", Microprocessors and Microsystems, 37(3), pp.299~312 (2013)
- J. Yoon, "A Bitstream Reverse Engineering Tool for FPGA Hardware Trojan Detection", Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, pp.2318~2320 (2018)
- T. Zhang, "A Comprehensive FPGA Reverse Engineering Tool-Chain : From Bitstream to RTL Code", IEEE Access, 7, pp.38379~38389 (2019)
- Lavin, Christopher, "Rapid prototyping tools for FPGA designs: RapidSmith", 2010 International Conference on Field-Programmable Technology (2010), IEEE
- Lavin, Christopher, "Rapidsmith: Do-it-yourself cad tools for xilinx fpgas", 2011 21st International Conference on Field Programmable Logic and Applications (2011), IEEE
- Malhotra, Shawn, "The quartus university interface program: enabling advanced fpga research", Proceedings of 2004 IEEE International Conference on Field-Programmable Technology (2004)
- M. Jeong, "Extract LUT Logics from a Downloaded Bitstream Data in FPGA", 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1~5 (2018)
- Moradi, Amir, "On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs", Proceedings of the 18th ACM conference on Computer and communications security (2011), ACM
- M. Young, "The Technical Writer’s Handbook" (1989), University Science