Design of a 128-bit AES Block Cipher Core
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Advanced encryption standard (AES), most widely used to encrypt and decrypt data, is computationally intensive algorithm. In order to implement the AES encryption algorithm, the data must go through complicated operations composed of several steps. The AES encryption algorithm is generally used for internet-based applications. In this paper, we propose the AES core, which selects the operation mode for the block cipher. Also, we implement the AES core by using an field programmable gate array (FPGA) and verify the functionality of the AES core with prototype board. The implementation results are obtained using the AES block cipher processors.
Abstract
Advanced encryption standard (AES), most widely used to encrypt and decrypt data, is computationally intensive algorithm. In order to implement the AES encryption algorithm, the data must go through complicated operations composed of several steps. The AES encryption algorithm is generally used for internet-based applications. In this paper, we propose the AES core, which selects the operation mode for the block cipher. Also, we implement the AES core by using an field programmable gate array (FPGA) and verify the functionality of the AES core with prototype board. The implementation results are obtained using the AES block cipher processors.