SEED 암호알고리즘의 Verilog HDL 구현을 위한 최적화 회로구조
An Optimal Circuit Structure for Implementing SEED Cipher Algorithm with Verilog HDL
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초록
This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.
Abstract
This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.
참고문헌 (10)
- 128비트 블록 암호알고리즘 (SEED) 개발 및 분석 보고서, "한국정보보호센터", 한국정보보호센터, ~ (1998)
- 전신우, "128비트 SEED 암호 알고리즘의고속처리를 위한 하드웨어 구현", 한국통신정보보호학회 논문지, 11(1), pp.13~23 (2001)
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- 송홍복, "SEED형식 암호에서 S박스와 G함수 구성에 관한 연구", 한국통신학회논문지, 27(4), pp.291~300 (2002), 한국통신학회
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- 엄성용, "SEED 블록 암호 알고리즘의 파이프라인 하드웨어 설계", 정보과학회논문지 : 시스템 및 이론, 30(4), pp.149~159 (2003), 한국정보과학회
- 박영호, "352-비트 암호 알고리즘의 하드웨어 설계", (사)디지털산업정보학회 논문지, 5(1), pp.51~61 (2009), (사)디지털산업정보학회
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- H. Feistel, "Block Cipher Cryptographic System", U. S. Patent, #3, 798, 359, ~ (1974)